100 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 8, NO. 1, JANUARY 2009 Low-Cost and Highly Heat Controllable Capacitorless PiFET (Partially Insulated FET) 1T DRAM for Embedded Memory Dong-il Bae, Sungho Kim, and Yang-Kyu Choi, Member, IEEE Abstract—A body-tied partial-insulated FET (PiFET) one- transistor (1T) DRAM having good heat immunity for embedded memory is proposed in this paper. PiFET structure using par- tially insulated oxide (PiOX) formed on bulk wafer can act as a 1T DRAM by applying a negative back bias. The memory shows a good “0”-state retention characteristic due to reduced electric field and heat dissipation path. The body-tied PiFET provides a wider design window and flexibility to control retention charac- teristics than does silicon on insulator (SOI) FET. To evaluate the improvement of retention characteristics, we suggest a new re- tention degradation mechanism of 1T DRAM. In this paper, we suggest the possibility of 1T DRAM’s fabrication having good heat immunity. Index Terms—Capacitorless embedded memory, one-transistor (1T) DRAM, partial-insulated FET (PiFET), retention, sensing margin. I. INTRODUCTION S INCE the concept of one-transistor (1T) capacitorless DRAM was proposed [1], it has been regarded as a promis- ing candidate to implement an embedded memory into a logic chip. Required specifications of the embedded memory are a small cell area, high process compatibility to a standard bulk MOSFET, low cost, good retention characteristics, and high im- munity to heat. To satisfy these demands, various kinds of 1T DRAM structures have been proposed. A conventional 1T DRAM formed on a partially depleted (PD) silicon on insulator (SOI) showed possibility of embedded memory [2]. A double- gate (DG) type 1T DRAM on a fully depleted (FD) SOI showed the capacity to suppress both short-channel effects and reten- tion degradation caused by trap-assisted tunneling [3]. Retention characteristics were sensitive to nondissipated heat because of the low thermal conductivity of the buried oxide underneath the channel in the SOI 1T DRAM. A new kind of 1T DRAM on a bulk wafer with high process compatibility to a bulk MOSFET was proposed to circumvent these problems [4]. There were another previous works that figured out that a major reason of the retention degradation is thermal generation, and “0”-state retention is more vulnerable at high temperature [5]. Manuscript received June 28, 2007; revised May 21, 2008; accepted July 27, 2008. First published September 26, 2008; current version published January 16, 2009. The review of this paper was arranged by Associate Editor T. Hiramoto. The authors are with the School of Electrical Engineering and Computer Sci- ence, Korea Advanced Institute of Science and Technology, Daejeon, 305-701, Korea (e-mail: equal72@nobelab.kaist.ac.kr; kkam226@gmail.com; ykchoi@ ee.kaist.ac.kr). Digital Object Identifier 10.1109/TNANO.2008.2006502 Fig. 1. Schematics of capacitorless 1T DRAM. (a) Conventional SOI 1T DRAM. (b) PiFET 1T DRAM. The PiOX and applied negative back bias isolate a channel from a body. In this paper, we suggest a new 1T DRAM structure using a PiFET, which has process compatibility to bulk wafer and good heat dissipation properties. We investigate a degradation mecha- nism of the retention with the aid of a commercialized simulation tool, Silvaco Atlas [6]. Improved retention characteristics com- pared to the conventional SOI 1T DRAM are observed in the simulation study. For this paper, an important new parameter, a retention factor (R F ) to identify the retention characteristics, is suggested. II. DEVICE STRUCTURE AND SIMULATION Fig. 1 shows a bird’s eye view of the conventional SOI and the body-tied PiFET [7] 1T DRAM structure used in device simu- lation. In the case of the body-tied PiFET 1T DRAM, electrical isolation between the channel and body is achieved by the PiOX located in the bottom of partial channel and negative back gate bias, as shown in Fig. 1(b). Electrical isolation makes quasi- SOI operation possible. Thus, an important difference between the two structures is the profile of isolation: one is the buried oxide (entirely insulated) and the other is the PiOX (partially insulated). All structures used in this paper are double-gate, and show a floating body effect, which is highly attractive for 1T DRAM operation. The PiFET structure has several advantages in terms of retention improvement. First, the nonoverlap region in the PiFET underneath source/drain (S/D) lowers the electri- cal potential by a reverse bias at the substrate, and act as heat dissipation path by discharging the accumulated holes, because 1536-125X/$25.00 © 2009 IEEE Authorized licensed use limited to: IEEE Xplore. Downloaded on January 28, 2009 at 00:13 from IEEE Xplore. Restrictions apply.