1056 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 7, JULY 2010 Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artiﬁcial Neural Networks V. Janakiraman, Amrutur Bharadwaj, and V. Visvanathan Abstract —Artiﬁcial neural networks (ANNs) have shown great promise in modeling circuit parameters for computer aided design applications. Leakage currents, which depend on process parameters, supply voltage and temperature can be modeled accurately with ANNs. However, the complex nature of the ANN model, with the standard sigmoidal activation functions, does not allow analytical expressions for its mean and variance. We propose the use of a new activation function that allows us to derive an analytical expression for the mean and a semi-analytical expression for the variance of the ANN-based leakage model. To the best of our knowledge this is the ﬁrst result in this direc- tion. Our neural network model also includes the voltage and temperature as input parameters, thereby enabling voltage and temperature aware statistical leakage analysis (SLA). All existing SLA frameworks are closely tied to the exponential polynomial leakage model and hence fail to work with sophisticated ANN models. In this paper, we also set up an SLA framework that can efﬁciently work with these ANN models. Results show that the cumulative distribution function of leakage current of ISCAS’85 circuits can be predicted accurately with the error in mean and standard deviation, compared to Monte Carlo-based simulations, being less than 1% and 2% respectively across a range of voltage and temperature values. Index Terms—Activation, leakage, log-normal, neural network, sigmoid, statistical. I. Introduction L EAKAGE power is approximately 50% of the total active power in the 90 nm technology node and is expected to remain a signiﬁcant fraction of the total active power in scaled technologies [1], [2]. Hence, it is important to accurately estimate the total leakage current of a digital circuit not only to estimate the total chip power, but also to design an effective power grid which can deliver the required active current. Leakage currents depend exponentially on certain process and environment parameters, like effective gate length, L e , Manuscript received May 19, 2009; revised October 15, 2009 and February 6, 2010. Date of current version June 18, 2010. This work was supported by the Department of Information Technology and Ministry of Communication, Government of India, India, for electronic design automation tools. This paper was recommended by Associate Editor D. Sylvester. V. Janakiraman and A. Bharadwaj are with the Department of Electrical and Communication Engineering, Indian Institute of Science, Bangalore 560012, India (e-mail: jramaanv@gmail.com; amrutur@ece.iisc.ernet.in). V. Visvanathan is with Texas Instruments, Bangalore 560093, India (e-mail: vish@ti.com). Color versions of one or more of the ﬁgures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identiﬁer 10.1109/TCAD.2010.2049059 oxide thickness, T OX , threshold voltage V TH and supply and temperature. Hence, even small variations in these show up as a large variation in the leakage current, with Borkar et al. in [3] reporting up to 20× variation in the leakage of manufactured chips. Process parameter variations consist of both die-to-die and within-die variations. Die-to-die (or inter-die or global) vari- ations affect all transistors within a die in the same way and are modeled as a single random variable which takes on the same value for each gate in the chip. Within-die (or intra- die or local) variations affect different gates within the same chip differently. These can have two components: a spatially correlated component and a random component. For spatially correlated variations, gates within a small region get affected identically. This effect is modeled by breaking the die into many regions, with one random variable per region [4]. The random variable takes on the same value for all the gates within the region. Random local variations affect each gate independently. In fact, their origin can be traced to random ﬂuctuations within each transistor’s gate length (LER), oxide thickness (OTV) and threshold voltage due to random dopant ﬂuctuations (RDF) [5], [6]. Atomistic simulations in [6] show that these ﬂuctuations become quite signiﬁcant in technologies below 35 nm, with standard deviation of threshold voltage reaching 100 mV for a nominally sized transistor in a 9 nm process node. In a chip consisting of millions of gates, one would expect that the impact of random local variations on leakage averages out. However, local variations increase the mean leakage signiﬁcantly due to the non-linear dependency of leakage on process parameters. Hence, an accurate analysis needs to incorporate the effect of these random local varia- tions. In the 100 nm node, Rao et al. in [7] show that, while global variations can cause a 14× variation in the leakage of a chip, local variations can cause a 3× variation, clearly indicating that local variations need to be modeled for accurate yield estimation in scaled technologies. Besides process variations, leakage current strongly depends on temperature and supply voltage. The heat dissipated by a block depends on its activity besides its leakage. Thus, there is a non-uniform temperature proﬁle across the chip based on the computational activity. Computationally intense blocks dissi- pate more heat and hence have a higher ambient temperature (100°C) while low-activity blocks like caches have a lower ambient temperature (50 °C) [3], [8]. Supply voltage is not 0278-0070/$26.00 c  2010 IEEE