International Journal of Computer Applications (0975 – 8887) Volume 55– No.7, October 2012 33 Probabilistic Defect Analysis Model for Quantum dot Cellular Automata Design at Analytical Phase Arijit Dey B.P.Poddar Institute of Management and Technology, 137, VIP Road, Kol-700052, India Kunal Das B.P.Poddar Institute of Management and Technology, 137, VIP Road, Kol-700052, India Debashis De West Bengal University of Technology, BF-142, Sector-I, Salt Lake City, Kolkata 700064, India Mallika De Department of Engg.and Technological Studies, Kalyani University, Kalyani 741235, West Bengal, India ABSTRACT The advantage of defect analysis on Quantum dot Cellular Automata(QCA) is that defects can be predict (which are probable to arise during fabrication phase) at analytical phase of QCA design. Since QCA is probabilistic in nature, the probability theory is introduced here to analyze the defect/fault tolerance at gate level of QCA design. We proposed a Bayesian network based Probabilistic Defect Analysis Model (PDAM) to analyze the defect at analytical phase of QCA design. Proposed model is applied over QCA wire, three input Majority voter, Five Input Majority voter and the result is compared with QCADesigner to justify the importance of PDAM approach over exhaustive simulation process with QCADesigner. Keywords Radius of effects; Five Input Majority Voter; Bayesian Network; PDA Model; Conditional probability 1. Introduction Quantum dot Cellular Automata (QCA) is becoming emerging technology in the field of nano scale computing. In 1993, C. S. Lent et al proposed the QCA as an alternative nano computing paradigm [1-3]. An exhaustive research is conceived during a decade and becomes research interest. Several proposals have been reported to design the QCA Device fabrication [4-5], Logic implementation [6-13], and testing [14-23] etc. the fundamental theory of computation for QCA is a cell, consisting of two extra electrons confined within square shape four quantum dot systems. The device cell design is such that (figure 1.a) the electrons (4M + 2) are confined within cell and can’t able to tunnel outside cell unlike with CMOS technology, where ‘M’ is number of electrons in each QD and ‘2’ is extra electrons injected (extra number). Due to the position of QD in a square shape cell (four corner of square) the two extra electrons have only two choices as shown in figure 1.b, these two state are denoted ‘+1.00’ polarization and ‘-1.00’ polarization and corresponding Logic state are defined as State 1 and 0. Logic gate design involved affect of neighboring cells coulumbic interaction (for example Majority Voter ‘MV’ shown in figure 1.c). The ground state configuration can be described by Knik energy. The Knik energy is inversely proportional to distance between two charge qi, qj defined as (1) Where ε0, εr are permittivity of free space and relative permittivity respectively. For QCA Logic gate design need four adiabatic clocking namely Relax, Switch, Hold and Release phase. This clock conflict can be the cause of error at gate level as well as circuit level. The 3 X 3 tile nano structure in QCA is found to be most promising design approach [16-18]. In early there are several proposal have reported. 3 X 3 tile structure is becoming empirical due to its robustness and versatile logic implacability. 3 X 3 tile structure can be classified in terms of active and passive categories. Active type 3 X 3 tile are those the computational part took place, namely orthogonal tile [17], triple input majority voter [17], five input majority voter [16,18], and coupled majority-minority voter [16]. On the other hand passive type are those no computation is took place rather processed by wire, passive type tile are namely double fan out tile [17], triple fan out tile [17], baseline tile [17], fan in tile [17], symmetrical-asymmetrical tile [17]. Defects are basically uncertainty, which is probable to occur in any VLSI design. QCA design is not also out of this list. The different issues in QCA defects are considers on chemical synthesis phase and deposition phase. The gate level and logic level, the defect test with exhaustive simulation is reported in early reports [16]. In this paper our attempt is to introduce probabilistic approach for defect analysis at analytical phase in QCA with an Artificial Intelligence tool Bayesian Network that permits probability and statistical method to deal with defects in QCA circuits. S. Bhanja et al. represents QCA circuit at layout level of Bayesian Network model[27-34].In this paper, the different probability of defect like extra cell deposition, Missing cell deposition, Misplacement of cell deposition at gate level has been studied. The Probabilistic Defect Analysis Model with Bayesian Network is reported. The comparison is made between exhaustive simulation result (with simulator QCA Designer [35]) and proposed Probabilistic Defect Analysis Model (PDAM). j i j i r kink j i q q r r E | | 4 1 0 ,    