A Tool for the Automatic TLM-to-RTL Conversion of Embedded Systems Requirements for a Seamless Veriﬁcation Flow Zeineb Bel Hadj Amor, Laurence Pierre, Dominique Borrione TIMA Laboratory (CNRS-INPG-UJF) 46 Avenue Felix Viallet, 38031 Grenoble France Zeineb.Bel-hadj-amor@imag.fr, Laurence.Pierre@imag.fr, Dominique.Borrione@imag.fr Abstract—Complex Systems on Chips (SoCs) are built by assembling hardware and software components. SystemC TLM (Transaction Level Modeling) allows to describe SoCs in a very abstract way. From this level, a typical design ﬂow enables the deﬁnition of virtual prototypes at different levels of abstraction to support early software development and veriﬁcation of hardware blocks which, in the last steps, become Register Transfer Level (RTL) models. A compatible and seamless veriﬁcation ﬂow must give the possibility to verify, along this design ﬂow, that the system requirements remain satisﬁed. To keep the requirements consistent with the abstraction level, we propose the automatic transformation of system level properties into their counterparts at the RT level. This paper describes a tool for the automatic reﬁnement of temporal assertions from TLM to RT level, using a set of transformation rules. This reuse of TLM assertions is thus the basis of an Assertion-Based Veriﬁcation (ABV) ﬂow. I. I NTRODUCTION The complexity of System-on-Chip (SoC) products has in- creased dramatically, making the use of RTL (Register Transfer Level) design methodologies tedious, time consuming, and error prone. Electronic System Level (ESL) methodology [1] combines the beneﬁts of increasing the design and veriﬁcation activities to a higher level, and of making the reuse of IP (In- tellectual Property) blocks easier. The ESL ﬂow complies with the need for hardware/software co-design and early functional veriﬁcation. Figure 1 shows a typical ESL design ﬂow as described by [2],[3]. Starting with a textual speciﬁcation, the ﬁrst step consists in obtaining a speciﬁcation of the entire system capturing the basic functionalities and requirements regardless of architectural and timing concerns. At this step, a preliminary analysis can be made to guide architectural decisions leading to Hardware/Software partitioning. The outcome is an archi- tectural speciﬁcation model. This system level architectural system is the virtual prototype for the software development path and the golden reference for the hardware design and veriﬁcation activities. Such a virtual platform can be material- ized as a SystemC transaction level modeling (SystemC-TLM) description. It has to be veriﬁed with respect to the original speciﬁcation and requirements. The system level architectural model will be incrementally reﬁned, giving rise to the RTL model for the hardware. The resulting implementation has to be veriﬁed with respect to the golden model. Fig. 1. Typical ESL design ﬂow [2] There are increasing demands for effective veriﬁcation ﬂows that can help to reduce the veriﬁcation cost. For example, [4] reports a recent study on the total percentage of project time spent in veriﬁcation: Figure 2 shows that in 2007, the average (mean) project time spent in veriﬁcation was 49 percent, while it increased to 56 percent in 2010 and 2012. Fig. 2. Percentage of total project time spent in veriﬁcation [4] In this context, Assertion-Based-Veriﬁcation (ABV), a well known veriﬁcation methodology for RTL models [5], has 978-1-4799-6016-3/14/$31.00 c  2014 IEEE