Modeling Monitors in VHDL Matthias Bauer, Jörg Böttger, Wolfgang Ecker, Peter Jensen Siemens AG, Corporate Research and Development, ZFE T SE 5 D-81730 Munich, Otto-Hahn-Ring 6 Email: matthias.bauer@zfe.siemens.de, wolfgang.ecker@zfe.siemens.de Abstract We present a template based approach for modeling monitors in VHDL with the intention to show a flexible VHDL system level modeling method. First an overview over existing approaches is given and the monitor approach is motivated. Second general software and VHDL aspects are discussed. Subsequent an application modeling of monitors in VHDL is shown. Finally we outlook towards protected Ada types, which have similar behavior as the planned VHDL shared variables. 1 Introduction 1.1 Design and Abstraction Top down design methodology is widely used to cope with design complexity. Specifications in the traditional sense document interim results of design stages in a natural language. These specifications grow with the com- plexity of the systems. Currently they are replaced by executable specifications, to make verification, valida- tion, and analysis of design steps and their results possible. Different approaches to abstraction are used to reduce the model expense of executable specifications, e.g.: • Explicitly described freedom like don’t care (‘-’). • Using statistic instead of functional models. • Considering performance aspects only. • Application of super symbols like records, subroutines or classes as known from software design. • Incompleteness by omitting partial behaviour like error cases or initialization by reset. • Abstraction in time, value, and description style. 1.2 Models for Abstraction A classification of design levels related to abstraction in time, value and description style was presented in [Ram91]. The design cube [EcHo92] defines these abstraction levels independently giving a three dimensional design space assigning each of them to the corresponding axes. Time abstractions namely propagation delay, clock relation and causality are seen as the most important factor in this model. A comparative study of differ- ent description or specification languages according to their abstraction mechanisms can be found in [NaGa93]. We will concentrate in the rest of the paper on VHDL based approaches only. 1.3 Related Work Special abstract modeling approaches, such as the use of Petri Nets [AbCo90, FRBC91, MüKr93, Ram93, SRAJ94, WiMo94], statistic system models [HuTo90], or performance models [CaHP95] are used for early system evaluation. Also the application of software techniques like structured analysis for early real time sys- tem modeling is applied [LSK91, SKS91]. Another approach to reduce modeling effort is the application of incomplete specification and incremental design as proposed in [Hoh91]. An application specific approach for architecture evaluation, considering full functionality and timing for anal- ysis, can be found in [PSL91]. Here timing and functionality are modeled in one run but a lot of modeling effort need to be spent. A new approach presented in [ScEc96] reduces the modeling expense for clock related description. However it still requires more model expense than pure causal description. An extended VHDL-subset for time abstraction is described in [BeSt91] and a pure VHDL based approach can be found in [EcMa93] and [HuDi95]. VHDL modeling of causal synchronization by using semaphores [Eck92] and data exchange by using communication channels and global memory [Wyt95, BaEc93] are the basis for systematic VHDL system level modeling. However, they restrict the application of VHDL to a set of pre- defined operations.