Digitally Enhanced Analog Circuits: System Aspects Boris Murmann Stanford University Department of Electrical Engineering Stanford, CA, USA murmann@stanford.edu Christian Vogel Graz University of Technology Signal Processing and Speech Communication Laboratory Graz, Austria vogel@tugraz.at Heinz Koeppl EPFL School of Communication and Computer Sciences Lausanne, Switzerland heinz.koeppl@epfl.ch Abstract— An overview of digital enhancement techniques for analog circuits is presented. Recent research suggests that the high density and low energy of digital circuits can be leveraged to enable a new generation of interface electronics that is based on minimal precision, low complexity analog blocks. Today, examples of enhancement schemes can be found in diverse applications and include nonlinearity compensation of ADCs, predistortion of power amplifiers and mismatch calibration in radio receivers. Since it is often difficult to identify commonalities among these different, but conceptually related schemes, this tutorial paper aims to provide a unified and system-oriented perspective of the field. I. INTRODUCTION The continuing downscaling of feature sizes in integrated circuits has enabled the realization of ever more complex electronic devices. In addition to purely digital functions such as microprocessors, we have seen an extraordinary growth in wireless and wireline communications. Since most communication channels are “analog” in nature, such applications are typically partitioned into an analog front-end and a digital back-end processing unit. Since the analog and digital system elements usually obey different limits and technology trends, proper partitioning is an important challenge. This is particularly so in cases where the analog interface constitutes the system’s bottleneck. In recent years, we have seen growing efforts to push the digital processing functions “closer to the antenna,” aiming for a reduction in the complexity of performance-limiting analog elements. In addition to minimizing analog content, there has been a clear trend toward digitally enhanced analog design, aiming to leverage digital correction and calibration techniques to improve the analog performance. Historically, digital enhancements to analog circuits have evolved at the block level of specific functions, as for example linearity calibration in A/D converters. In this classical scenario, digital correction is more or less applied as an afterthought and without considering the overall system. With the growing complexity in today’s applications, there exists an opportunity to explore a more holistic view of digital correction; one that looks at block interplay, and specific system and signal attributes. Figure 1 shows a general block diagram of a digitally enhanced electronic system in which additional digital resources are allocated either to assist individual blocks or to facilitate the system-wide interaction of previously isolated blocks. Digital Signal Processing A/D D/A Signal Conditioning Signal Conditioning Analog Media and Transducers CLK Digital Enhancement Digital Enhancement Figure 1. Block diagram of a generic electronic system with digital enhancement. The purpose of this paper is to provide an overview of the state-of-the-art in digital enhancement techniques, highlighting challenges and opportunities from a system-level perspective. We begin our discussion by outlining the tradeoffs and scaling trends of analog and digital circuits in Section II. Section III identifies the different hierarchical levels at which digital enhancement can be used. Section IV provides additional examples and insight into specific applications. II. CIRCUIT LEVEL CONSIDERATIONS A. Digital Logic Over the past decades, integrated circuit technology has been scaled according to Moore’s law, aiming to double the number of transistors per die every two years. A direct result of this scaling trajectory has been the tremendous improvement in the performance of digital circuits. For instance, lead microprocessors have shown a doubling in their computing power roughly every 15 months. Alongside with these improvements in speed comes a significant reduction in