218 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 60, NO. 2, FEBRUARY 2012 ParAFEMCap: A Parallel Adaptive Finite-Element Method for 3-D VLSI Interconnect Capacitance Extraction Genlong Chen, Hengliang Zhu, Member, IEEE, Tao Cui, Zhiming Chen, Xuan Zeng, Member, IEEE, and Wei Cai Abstract—Parasitic extraction is one of the key techniques in very large scale integration design that has been widely used to build the equivalent-circuit model of interconnects. In this paper, a parallel adaptive finite-element method (AFEM) for capacitance extraction of large-scale interconnects (ParAFEMCap) is devel- oped to provide extremely high parallel scalability and numerical accuracy. First, the proposed ParAFEMCap has the potential of high parallel scalability by taking advantages of several advanced parallel techniques, such as parallel adaptive mesh refinement and dynamic load balancing. To the best of the authors’ knowledge, this is the first capacitance extraction field solver that is able to run in parallel on hundreds and even thousands of CPU cores. Second, the proposed ParAFEMCap is based on the AFEM, which is proven to converge to the exact solution of the electromagnetic problems in a theoretically quasi-optimal rate. The solution pre- cision of ParAFEMCap can easily be controlled by varying the threshold for the a posteriori error estimator, while the computa- tional time can easily be reduced by increasing the number of CPU cores. Moreover, ParAFEMCap is shown to have the same linear computation complexity as those integral-equation methods, which make it very promising for capacitance extraction of large-scale interconnect problems. Numerical experiments will demonstrate that ParAFEMCap has the advantages of high computational effi- ciency and accuracy for solving the capacitance extraction problem of large-scale interconnects with complex multilayer structures. Index Terms—Capacitance extraction, interconnect modeling, parallel adaptive finite-element method (AFEM). Manuscript received April 21, 2011; revised October 07, 2011; accepted Oc- tober 20, 2011. Date of publication December 16, 2011; date of current ver- sion February 03, 2012. This work was supported in part by the National Basic Research Program of China under Grant 2011CB309701, the National Natural Science Foundation of China (NSFC) Research Project under Grant 60976034, Grant 61076033, Grant 61125401, and Grant 61106032, by the National Major Science and Technology Special Project (Grant no. 2009ZX02023-4-3) of China during the 11th five-year plan period, by the National Major Science and Tech- nology Special Project (Grant no. 2011ZX01035-001-001-003) of China during the 12th five-year plan period, by the Doctoral Program Foundation of the Min- istry of Education of China under Grant 200802460068, by the Program for Out- standing Academic Leader Shanghai, by the China Postdoctoral Science Foun- dation, by the Department of Energy (DOE) under Grant DEFG0205ER25678, and by the National Science Foundation (NSF) under Grant DMS-1005441. G. Chen, H. Zhu, and X. Zeng are with the State Key Laboratory of ASIC & System, Microelectronics Department, Fudan University, Shanghai 200438, China (e-mail: hlzhu@fudan.edu.cn; xzeng@fudan.edu.cn). T. Cui and Z. Chen are with the State Key Laboratory of Scientific and Engi- neering Computing (LSEC), Institute of Computational Mathematics, Academy of Mathematics and System Sciences, Chinese Academy of Sciences, Beijing 100190, China. W. Cai is with the Department of Mathematics, University of North Carolina, Charlotte, NC 28223-0001 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2011.2176137 I. INTRODUCTION A S THE very large scale integration (VLSI) technology scales down to nanoscale and the circuit frequency reaches gigahertz, interconnects play a more and more impor- tant role in today’s integrated circuits (ICs). The parasitic effects of interconnects could greatly deteriorate the performance of the circuits and lead to many signal integrity problems. Parasitic extraction of interconnects, which builds the equivalent-circuit model for interconnects by various numerical approaches, therefore becomes one of the key steps in IC design [1]. The problem of parasitic extraction of interconnects has been studied for almost three decades. Most of the research mainly fall into three categories, namely: 1) capacitance extraction [2]; 2) inductance extraction [3], [4]; and 3) full-wave impedance extraction [5], [6]. The inductance extraction and full-wave impedance extraction that also account for the skin effect and eddy-current effect of the nonideal conductors have higher accuracy, and is widely used in analog circuit and microwave circuit design. While in digital circuit design, higher order effects like eddy currents are generally neglected to reduce the computational cost and the parasitic capacitance model is gen- erally applied. The major challenge of digital circuit design is its large-scale and complicated structure, which greatly reduces the accuracy and efficiency of capacitance extraction. Fast and accurate extraction of interconnects is only available for interconnects with relatively small and simple structures. For large-scale interconnects with complex multilayer structures, efficient capacitance extraction tools that are able to provide accurate results are very important, especially in the case that we want to accurately calculate the delay of a critical path that might involve a relatively large and complex interconnect structure. On the other hand, the evolution of the high-per- formance computer provides a potential remedy to solve the computational bottleneck. Due to its high parallel scalability and flexibility, parallel finite-element method (FEM) [7], [8] becomes a promising method for parallel parasitic extraction of interconnects with a complex multilayer structure. Most of the capacitance extraction methods proposed thus far are based on the so-called “field solver,” which falls into two categories, i.e., the integral-equation methods [2], [9], [10] and the differential-equation methods [11], [12]. Generally, the integral-equation methods are based on the boundary-element method (BEM), which formulates the unknowns on the con- ductor surfaces and the dielectric interfaces. One of the advan- tages of integral-equation methods is that the size of the resulted 0018-9480/$26.00 © 2011 IEEE