Realization of Adaptive Filter using Vedic Multiplier A.Kamaraj 1 , C.Kalyana Sundaram 2 , J.Senthil Kumar 3 Electronics and Communication Engineering, Mepco Schlenk Engineering College Sivakasi, India 1 kamarajme2006@yahoo.com 2 gullycks.kalyan@gmail.com 3 senvimjag@gmail.com Abstract— The principal technique proposed in this paper is the use of Vedic Multiplier in Adaptive Filter design. The design of Adaptive Filter using LMS (Least Mean Square) algorithm is the prime step involved and the Vedic Multiplier is incorporated in updating filter coefficients and in the computation of filter output. Furthermore, Vedic Multiplier reduces the delay involved in Robertson multiplication process. Tracking speed and stability of the Adaptive Gradient Filtering algorithms are analysed by designing Adaptive Filter in Verilog language and realizing in Spartan 3E kit. Keywords— Adaptive Filter, LMS, Step size, Urdhva Tiryagbhyam Sutra, Vedic Multiplier. I. INTRODUCTION The significance of the implementation of Adaptive Filter can be noted as it persists in commonly visible devices such as mobile phones, camcorders, digital cameras, medical monitoring equipment etc. In the process of transmission of information from the source to receiver side in all channels, noise from the surroundings automatically gets added to the signal. The problem of effective removal or reduction of noise is an active area of research. The usage of Adaptive Filter is one of the most popular proposed solutions. Adaptive Filter self-adjusts its transfer function according to the optimization algorithm used [3]. Adaptive Filter uses error signal as feedback and accordingly updates the filter coefficients. A non-adaptive Filter has a static transfer function, whereas the transfer function of the Adaptive Filter continuously changes. Because of the overall performance and construction flexibility, Adaptive Filters have been employed in many different applications; some of the most important are telephonic echo cancellation, noise cancellation, system identification, communication channel equalization and biometrics signal processing [3]. The reason behind the use of Vedic Mathematics in multiplier design lies in the fact that it reduces the cumbersome looking calculations in conventional mathematics to a very simple one. It has many conventional Sutras and they can be applied to cover each and every part of mathematics including arithmetic, algebra, geometry, trigonometry, astronomy, calculus etc. This is a very interesting field and presents some effective algorithms which can be applied to various branches of engineering such as computing and digital signal processing [1]. Minimizing power consumption for digital systems involves optimization at all levels of the design. This optimization includes the technology used to implement the digital circuits, the circuit style and topology, the architecture for implementing the circuits and at the highest level the algorithms that are being implemented. So in this paper, we investigate the efficiency of Vedic multiplier in terms of combinational path delay involved. II. PROPOSED VEDIC MULTIPLIER Vedic Maths is a part of four Vedas. The word “Vedic” is derived from the word “Veda”, which means the store-house of all knowledge. Vedic Maths is mainly based on 16 Sutras. Among them, the fourteenth one is ‘Urdhva Tiryagbhyam – Vertically and Crosswise Sutra’ [1]. The application of this Sutra can be quite seen in the design of N*N multiplier. A. Urdhva Tiryagbhyam Sutra The ‘Urdhva Tiryagbhyam’ Sutra is based on parallel generation of partial products and concurrent addition respectively which is very different from the normal partial product method using shift and add operations (Robertson Multiplier) [7]. This Sutra has been traditionally used for the multiplication of two numbers in the decimal number system [9]. Here, we apply this Sutra to the binary number system. The motivation behind the extension to binary number system is to make it compatible with the digital hardware circuits. This Sutra is illustrated with the help of the multiplication of two 4-bit binary numbers. B. Line Diagram of Vedic Multiplier When N*N multiplier is implemented using Line diagram, the use of N*1 multiplier for generating a partial product can be replaced by N ‘logical and’ gates. The shifters can be replaced by using N half adders, N*(N-2) full adders, that is N*(N-1) adders. The results of the 2N-1 steps of the line diagram are presented in Figure 1. C. Architecture of Vedic Multiplier The N*N multiplier can be implemented using four (N/2)*(N/2) multipliers, a N bit adder, a N+1 bit adder and a Carry Save Adder for adding three N bit numbers [2]. The Carry Save Adder can be replaced by an ordinary adder for adding three N bit numbers, so that the architecture of N*N