Realizing high breakdown voltages (>600 V) in partial SOI technology Ramakrishna Tadikonda * , Shyam Hardikar, E.M. Sankara Narayanan Emerging Technologies Research Centre, De Montfort University, The Gateway, Leicester LE1 9BH, UK Received 6 January 2004; received in revised form 7 April 2004; accepted 8 April 2004 Available online 7 May 2004 The review of this paper was arranged by Prof. S. Cristoloveanu Abstract A combination of uniform and variation in lateral doping (UVLD) profiles is proposed for the drift region of lateral power devices in partial SOI (PSOI) technology in order to achieve breakdown voltages above 600 V. LDMOS transistor structures incorporating the proposed doping profile are analyzed for their electrical characteristics and compared with conventional uniformly doped PSOI and thin layer SOI by extensive 2-D numerical simulations using MEDICI. The results indicate that the proposed doping profile can significantly improve the trade-off between breakdown voltage and specific on-resistance as well as the heat dissipation in comparison to uniformly doped PSOI and thin layer VLD SOI. Ó 2004 Elsevier Ltd. All rights reserved. Keywords: Partial SOI; VLD; LDMOS; High voltage; Power IC; Self-heating 1. Introduction Silicon on insulator (SOI) technologies offer tre- mendous advantages over junction isolation (JI), such as low leakage current, near ideal isolation between de- vices, operation at higher environmental temperatures, considerable reduction in parasitic capacitance and higher switching speed [1] for power and high voltage ICs. However, due to the poor thermal conductivity of the buried oxide, self-heating can affect the device per- formance in SOI technology [2]. In contrast to SOI technology, the buried oxide in partial SOI (PSOI) is patterned to have a silicon window that connect the active region to the substrate offering a heat conduction path, thereby resulting in reduced self-heating while achieving a high breakdown voltage [3,4]. The location of the silicon window determines the potential distri- butionandhencetheblockingvoltagecapability.Device structures with silicon window underneath the drain show potential distribution similar to that in JI tech- nology and therefore, thickness of the buried oxide layer does not influence the breakdown significantly [5]. Consequently, thinner buried oxide layers can be used, which can alleviate self-heating significantly and reduce the on-resistance [6]. In device structures with silicon window underneath the source, both the JI and SOI regions influence the potential distribution with the SOI region having a similar potential distribution as a SOI device. Therefore, increasing the thickness of the buried oxide increases the breakdown voltage as in SOI technology. Consequently, the breakdown voltage in this case is higher with the window underneath the drain [5]. Furthermore, the sharing of potential across the buried oxide and substrate results in higher breakdown voltage for similar SOI thickness in comparison to SOI device where most of the applied voltage is supported by the BOX. However, breakdown voltages (BV) higher * Corresponding author. Tel.: +44-116-250-6157; fax: +44- 116-250-6158. E-mail address: raman@dmu.ac.uk (R. Tadikonda). 0038-1101/$ - see front matter Ó 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2004.04.005 Solid-State Electronics 48 (2004) 1655–1660 www.elsevier.com/locate/sse