IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 1, JANUARY 2006 287 3 Gb/s AC Coupled Chip-to-Chip Communication Using a Low Swing Pulse Receiver Lei Luo, John M. Wilson, Stephen E. Mick, Jian Xu, Liang Zhang, and Paul D. Franzon, Fellow, IEEE Abstract—A 120-mV low swing pulse receiver is presented for AC coupled interconnect (ACCI). Using this receiver, 3 Gb/s chip-to-chip communication is demonstrated through a wire- bonded ACCI channel with 150-fF coupling capacitors, across 15-cm FR4 microstrip lines. A test chip was fabricated in TSMC 0.18- m CMOS technology and the driver and pulse receiver dissipate 15-mW power per I/O at 3 Gb/s, with a bit error rate less than 10 . First-time demonstration of a flip-chip ACCI is also presented, with both the AC and DC connections successfully integrated between the flipped chip and the multichip module (MCM) substrate by using the buried bump technology. For the flip-chip ACCI, 2.5 Gb/s/channel communication is demonstrated across 5.6 cm of transmission line on a MCM substrate. Index Terms—AC coupled interconnect, bandlimited communi- cations, buried bump technology, capacitive coupling, multichip modules, pulse receiver, pulse signaling. I. INTRODUCTION T ECHNOLOGY scaling demands high-density and low- power off-chip input/output (I/O). The ITRS predicts the need for a 110- m pad pitch for cost-performance area array flip-chip applications in 2008 [1], a pitch that is difficult to achieve with available technologies. Recently, several technolo- gies have been reported using capacitive coupling to replace physical pin/solder bumps for high-density, low-power chip-to- chip communications [3]–[8]. This is based on the fact that non- contacting AC connections can be built more densely than DC connections and the AC component actually carries all the infor- mation of a digital signal. Instead of using traditional bonding wires as the DC connections at edge of chips, in AC coupled in- terconnect (ACCI), the buried solder bump technology provides a solution for both high-density signal I/O and power/ground pin distribution [4]. In contrast to most of the recent results focusing on stacked ICs [5]–[7], the work presented here, ACCI, is optimized for lossy, board-level, capacitively-coupled interconnect. This work enables long distance communication among multiple chips, while retaining the high-density and low-power properties of capacitive coupling. ACCI can not only satisfy the increasing demand for high-density signal I/Os, but it also saves precious Manuscript received May 15, 2005; revised August 15, 2005. This work was supported in part by the AFRL under Contract F29601-03-3-0135, in part by SRC under Task 1094, and in part by the National Science Foundation under Grant CCR-0219567. The authors are with the Department of Electrical and Computer Engi- neering, North Carolina State University, Raleigh, NC 27695 USA (e-mail: lluo3@ncsu.edu; jmwilson@ncsu.edu; semick@ncsu.edu; jxu6@ncsu.edu; lzhang3@ncsu.edu; paulf@ncsu.edu). Digital Object Identifier 10.1109/JSSC.2005.859881 Fig. 1. Comparison with previous CMOS high-speed pulse receivers. (All scaled to 0.18 m. To be on the same base line, single-ended is used for single-ended pulse receivers in [4]–[7]; differential is used for differential pulse receivers in [2] and in this paper). chip area for more / pins to improve power system signal integrity. In this paper, the unique band-pass channel response and equalization scheme of ACCI channel are discussed and com- pared with the traditional low-pass response of a transmission line (T-line) channel. Coupling capacitor and T-line design rules and design margins are discussed. A voltage-mode driver is used for the ACCI channel and saves more than 70% power, when compared to a traditional current-mode driver with conductive signaling. Interconnect power dissipation is mini- mized by using low swing-pulse signaling. For receiver design, previous CMOS single-ended [4], [5], [7] and differential [2] pulse receivers are reported with more than 200-mV input swing when scaled to 0.18- m technology, as shown in Fig. 1. In this paper, a 3-Gb/s differential pulse receiver requiring only 120 mV input swing is proposed. The three times reduction of input swing made possible by this receiver enables ACCI with a five times smaller coupling capacitance which translates to a five times higher I/O density, and a signal across longer T-lines than the previous work [4]. Chip-to-chip communication at 3 Gb/s is demonstrated through two 150-fF coupling capacitors across a 15-cm FR4 microstrip line. On the test chip, the pulse receiver converts pulses into nonreturn-to-zero (NRZ) data without a clock signal; then a semidigital dual DLL successfully recovers the receiver-side clock phase from the recovered NRZ data. An on-chip BER tester indicates errors less than 10 through one ACCI channel for rates up to 3 Gb/s. Given the density made possible by ACCI with this pulse receiver, the ITRS milestone of a 110- m pad pitch can be achieved. In addition, a flip-chip demonstration of ACCI is presented to show the feasibility of creating coupling capacitors and buried bumps across the same interface—between chip and 0018-9200/$20.00 © 2006 IEEE