HIGH-LEVEL MULTI-STEP INVERTER OPTIMIZATION, USING A MINIMUM NUMBER OF POWER TRANSISTORS. Juan Dixon (SM) Luis Morán (F) Department of Electrical Engineering Department of Electrical Engineering Pontificia Universidad Católica de Chile Universidad de Concepción Casilla 306, Correo 22, Santiago, Chile fax 56-2-552-2563 e-mail jdixon@ing.puc.cl (corresponding autor) Casilla 53-C, Concepción, Chile fax 56-41-246-999 e-mail lmoran@renoir.die.udec.cl ABSTRACT Multilevel inverters with a large number of steps (more than 50 levels) can generate high quality voltage waveforms, good enough to be considered as suitable voltage template generators. Many levels or steps can follow a voltage reference with accuracy, and with the advantage that the generated voltage can be modulated in amplitude (AM) instead than PWM. The main disadvantage of this type of topology is the large number of power supplies and semiconductors required to obtain these multi-step voltage waveforms. This paper is focussed in minimizing the number of power supplies and semiconductors (transistors or GTOs) for a given number of levels. Different combinations of topologies are presented, and the corresponding mathematical relations have been derived. The paper shows optimized curves to obtain the relation between minimum number of power semiconductors required for a given number of levels. Experimental results obtained from an optimised prototype, capable to generate 81 levels of voltage with only four power supplies and sixteen transistors per phase are shown.