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Sci., vol. 42, pp. 142–150, 1996. Similarity Searching for Defective Wafer Bin Maps in Semiconductor Manufacturing Chung-Shou Liao, Member, IEEE, Tsung-Jung Hsieh, Yu-Syuan Huang, and Chen-Fu Chien, Member, IEEE Abstract—Because high-dimensional wafer bin maps (WBMs) cause var- ious features, it is difficult to search the similarity among WBMs via con- ventional pattern recognition methods. This study develops a novel mor- phology-based support vector machine for defective wafer detection. The experimental results demonstrate its usefulness in yield improvements on precision and computation cost. Note to Practitioners—Semiconductor manufacturing in complicated nanotechnology is facing tough challenge for quick response to yield excursion for shortening time to market and reducing the cost to maintain competitive advantages. Due to the increasing complexity of nanotech- nology for wafer fabrication, increasingly high inspection costs and yield loss associated with defective wafers have become a critical concern of semiconductor manufacturers. Focused on real settings of practical industrial experiments, this study provides a novel approach to searching similar WBMs from huge wafer spatial data to quickly identify potential causes for yield enhancement. This approach was validated in real setting in Taiwan and the results showed its practical viability. Index Terms—Data mining, morphology, semiconductor manufacturing, similarity search, support vector machines, wafer bin maps. I. INTRODUCTION With increasingly sophisticated manufacturing processes in the semiconductor industry, the cost to migrate the required techniques Manuscript received May 02, 2013; accepted July 15, 2013. Date of pub- lication August 29, 2013; date of current version June 30, 2014. This paper was recommended for publication by Associate Editor S. Zhou and Editor H. Ding upon evaluation of the reviewers’ comments. This work was supported by the Advanced Manufacturing and Service Management Research Center, National Tsing Hua University under Toward World-Class Universities Projects 101N2073E1, 101N2074E1 and the National Science Council of Taiwan under Grant NSC100-2221-E-007-108-MY3, Grant NSC100-2628-E-007-017-MY3, and Grant NSC102-2221-E-007-075-MY3. (Corresponding author: C.-S. Liao.) The authors are with the Department of Industrial Engineering and Engineering Management, National Tsing Hua University, Hsinchu 300, Taiwan (e-mail: csliao@ie.nthu.edu.tw; tsungjung.hsieh@gmail.com; s9934519@m99.nthu.edu.tw; cfchien@mx.nthu.edu.tw). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TASE.2013.2277603 Fig. 1. An example of defective wafer bin maps: functional bins; defective bins. adds substantially to semiconductor production costs. Indeed, for the semiconductor industry as wafer production and size continues to grow, the volume of in-line and off-line data required to diagnose yield conditions is growing exponentially. Furthermore, high-volume wafer fabrication facilities typically produce thousands of wafers per week, and many of these wafers are inspected and found to be defective [1], [2], [3]. In this scenario, yield improvement is critically important, as is maintaining competitive processes and low die costs for semiconductor wafers in a fabrication facility. During the final process of wafer fabrication, Circuit Probe (CP) test will determine whether the corresponding die is good for packaging into chip. Spatial patterns of testing results are WBMs that provide crucial information to identify process failures, as illustrated in Fig. 1. These patterns are formed by marking the defective wafers, so that manufacturing engineers may use the patterns of WBMs as clues to investigate the causes of failures resulting in yield losses. As there are many WBMs to be evaluated, the judgments in semiconductor manu- facturing thus far still rely on human labor. As a result, the judgments may be inconsistent owing to human factors (e.g., fatigue) because of the substantial workload. In particular, not only should the defective dies be detected before package, but assignable causes should also be attributed to reduce yield and profit loss due to scrapped wafers. During the CP test, wafers are inspected by retrieving information about defect patterns [4]. More pre- cisely, WBM patterns can provide information to help better monitor the processes and products. The WBMs, in many cases, contain charac- teristic patterns, or signatures, which provide insight into the fitness of the manufacturing processes. A bin can be conceptualized as a bucket and viewed by mapping the results of these electrical tests onto a 2-D space. These defective patterns are usually associated with specific man- ufacturing problems, and can provide process and product engineers with important clues regarding the identification of causes and their so- lutions in order to improve yields [5]. Stapper [6] indicated that defects are typically clustered, rather than dispersed randomly over a wafer, and that these clusters become more evident as the wafer size increases. In the literature, the three proposed approaches to solving the pattern recognition problem are stated as: the statistical approach, the heuristic approach, and the simulation approach [7]. The statistical approach classifies patterns based on an extracted feature set, and an underlying statistical model for generating these patterns. The heuristic approach 1545-5955 © 2013 IEEE. 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