A Unified Model for Filter Capacitor Constraints in DC to DC Switching Converters Design A. Cantillo, A. De Nardo, N. Femia, W. Zamboni Dipartimento di Ingegneria dell’Informazione ed Ingegneria Elettrica (DIIIE) Università degli Studi di Salerno Fisciano (SA), Italy {acantillo,adenardo,femia,wzamboni}@unisa.it Abstract— This paper discusses a unified model for the determination of the constraint equations to be used in the selection of feasible capacitors for DC to DC converters. The model is based on a generalized waveform of the current flowing through capacitors, which provides the maximum acceptable ESR as a function of the capacitance C ensuring the compliance with ripple and constraints determined by the application. Design examples are presented regarding the application of the proposed model to boost, buck-boost and SEPIC topologies. I. INTRODUCTION The selection of filter capacitors is one of the major steps in the design of the power section of switching converters. The choice of filter capacitors may highly influence the size, the cost and the overall static and dynamic behavior of the converter. One of the main goals is to keep the filter capacitor as small as possible, compatibly with reliability and robustness needs. The maximum value ESR max and the minimum value C min can be determined by means of simplified approaches, like the ones indicated in textbooks [1- 2], scientific papers [3-4], and IC manufacturers technical literature [5], which provide very simple formulas, where ESR max and C min are independent. For example, referring to boost converter, if Δv opp and Δv ipp are respectively the maximum allowed output and input ripple, Δi Lpp and I o are ripple inductor current and load current, f s is the switching frequency, D is the duty-cycle, the following constraints are usually adopted for selecting input capacitors: Lpp ipp i i v ESR Δ Δ = max ; ipp s Lpp i v f i C Δ Δ = 8 min (1) and output capacitor: 2 / ' / 2 1 max Lpp o opp o i D I v ESR Δ + Δ = ; opp s o i v f DI C Δ = 2 / 1 min (2) Some inconveniencies may derive from the use of such formulas. As an example, for the input capacitor, formulas (1) are determined by assuming that the full voltage ripple is sustained both by the ESR and by the capacitance C as the two components of the ripple determined by ESR and C are orthogonal. Such assumption may lead to an undersizing of the capacitor. For the output capacitor, instead, formulas (2) are based on the assumption that the total voltage ripple is equally divided between the ESR and the capacitance C. This may lead to an oversizing of the capacitor. In general, simplified formulas imply an a priori allocation of a certain fraction of ripple to the ESR and to the capacitance C. In [6-8] it was shown that an accurate ripple analysis allows to consider the correlation existing between ESR and C to get more accurate and reliable design formulas wherein ESR max is a function of C. In this paper, that approach is generalized by introducing a unified model based on a general definition of the current waveform flowing in the capacitor which covers all the applications related to DC to DC converters. Thus, the peak-to-peak ripple voltage is determined as a function of ESR and C. Inverting the ripple equation provides the exact expression of ESR max as a function of C. Examples of such modeling approach are presented in the paper, regarding buck, buck-boost and SEPIC topologies. II. GENERALIZED CAPACITOR WAVEFORMS Let us consider DC to DC converters in steady-state continuous conduction mode, characterized by a switching period T s and a duty-cycle D. Let T 1 and T 2 be the time intervals [0, DT s ] and [DT s , T s ], respectively. It is reasonable to assume that: i) the currents flowing through the inductors are continuous and piecewise linear functions of time; ii) the currents flowing through the switches vanish either in T 1 or in T 2 . Additionally, we make the following hypothesis: iii) the switches are ideal (they are equivalent to a short- circuit in T 1 and to an open-circuit in T 2 , or vice- versa); iv) input voltage source is ideal and the converter input current is piecewise linear; 978-1-4244-5091-6/09/$25.00 ©2009 IEEE 295