© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim 7170 wileyonlinelibrary.com COMMUNICATION Charge-Trap Flash-Memory Oxide Transistors Enabled by Copper–Zirconia Composites Kang-Jun Baeg, Myung-Gil Kim, Charles K. Song, Xinge Yu, Antonio Facchetti,* and Tobin J. Marks* Dr. K.-J. Baeg, [+] Dr. M.-G. Kim, C. K. Song, X. Yu, Prof. T. J. Marks Department of Chemistry and the Materials Research Center Northwestern University 2145 Sheridan Road, Evanston, IL 60208, USA E-mail: t-marks@northwestern.edu Dr. M.-G. Kim Department of Chemistry Chung-Ang University 84 Heukseok-ro, Dongjak-gu, Seoul 156–756, Republic of Korea Dr. A. Facchetti Polyera Corporation 8045 Lamon Avenue Skokie, IL 60077, USA E-mail: a-facchetti@northwestern.edu DOI: 10.1002/adma.201401354 chip size and increased memory capacity at a reduced product cost, and iii) improved reliability at higher yields since the dis- crete traps are less susceptible to point defects in the tunnel oxide layer. [24] These aspects make CTF a state-of-the-art NAND (negated AND) ﬂash technology, currently enabling small fea- ture sizes (<20 nm) for both planar and vertical 3D memories. Since Si 3 N 4 —the material of choice for current CTFs— cannot be printed, it is unsuitable for emerging printed elec- tronic products. Thus, new solution-processable charge-trap materials are needed for new low-cost CTF memories. Here we report a solution-processed TFT-based memory device based on either low-temperature combustion-processed polycrystal- line (In 2 O 3 ) or amorphous (In-Ga-O) MO semiconductor ﬁlms, combined with a solution-processed copper-doped zirconium oxide (Cu-ZrO 2 ) composite/solid solution, which acts as an electrochemical redox trap layer. While CuO/Cu 2 O [25–27] or Cu- doped alumina (Al 2 O x ) [28] fabricated by physical vapor deposi- tion has been used as a charge-trapping layer in two-terminal resistive memories, to the best of our knowledge, solution-pro- cessed Cu-ZrO 2 has never been used in non-volatile transistor memory devices for CTF memories. This new approach enables high electron mobility and reliability, and when implemented with a high-capacitance self-assembled nano-dielectric (SAND), very low-voltage-operating (<3 V) CTF memories are produced. As shown in Figure 1, the present devices consist of a Si(n ++ ) back-gate, a charge-blocking dielectric layer, a charge-trap layer, a carrier-tunneling layer, a MO semiconductor channel, and Al source/drain electrodes. Between the charge-blocking and -tunneling dielectric layers, discrete charge-trap sites must be incorporated for stable data storage. This plays a similar role as in traditional ﬂoating-gates to shield the gate electric ﬁeld and modulate the channel conductance as a function of the charge- trap density. As a ﬁrst step, the representative MO semiconduc- tors, indium oxide (In 2 O 3 ) and indium–gallium–oxide (In-Ga-O), were selected since they can be processed at low temperatures using combustion techniques, affording polycrystalline [14] and amorphous ﬁlms, [29] respectively. These semiconductors are compatible with several gate dielectrics, and afford respect- able ON-currents and carrier mobilities (2–20 cm 2 V -1 s -1 ) for low ﬁlm growth temperatures (250–300 °C; see Sup- porting Information (SI): Figures S1 and S2 and Table S1). As an example, the In 2 O 3 TFTs fabricated here as control devices (annealed at 250 °C) have thin-ﬁlm electron mobilities of ∼2.2, ∼13.4, and ∼16.3 cm 2 V -1 s -1 when grown on SiO 2 (300 nm), ZrO 2 (24 nm), and Zr-SAND (∼11 nm) gate dielectrics, respec- tively. The mobility increase for MO TFTs with increased gate dielectric capacitance is characteristic of disordered semicon- ductors having a single exponential density of states (DOS) for the localized states. [30] Although several interpretations remain, Solution-processed metal–oxide (MO) semiconductors enable a variety of novel opto-electronic applications including those achievable via the printing processes of graphic arts. [1–7] Recent studies employing sputtered [8–10] or printable MOs have mainly focused on developing high-performance channel materials with high charge carrier mobilities, [11,12] low-temperature pro- cessability, [3,13,14] and robust operational stability. [15–18] There- fore, high-speed thin-ﬁlm transistors (TFTs) based on MOs will ﬁrst ﬁnd application in the back-plane of active matrix displays [19] and, eventually, transparent/ﬂexible displays and microprocessors for circuit drivers and radio-frequency identi- ﬁcation (RFID) tags. [20] Note also that random access memory (RAM) is another fundamental building block that is essential for storing programs or data in all logic circuitry. [21] For RAM fabrication, ﬂash memory is the most common conﬁguration because of its excellent compatibility with peripheral comple- mentary metal–oxide semiconductor (CMOS) circuits which address each memory cell, its reliable/uniform memory char- acteristics, its fast switching time, and its non-destructive read- out during the reading process. [22] Charge storage in a ﬂash memory relies on trapped charge carriers in the ﬂoating-gate (traditional poly-Si or nano-ﬂoating- gates) within a gate dielectric layer. [23] Charge-trap ﬂash (CTF) is another type of ﬂash memory technology which typically uses a non-conductive trap layer (e.g., Si 3 N 4 ) as a discrete electron- trapping layer rather than a ﬂoating-gate structure. [24] Com- pared to traditional ﬂash memory, CTF has numerous attrac- tions including: i) reduced fabrication steps to create a charge storage node, ii) smaller process geometries enabling reduced [+] Present address: Nanocarbon Materials Research Group, Korea Electro- technology Research Institute (KERI), 12 Bulmosan-ro 10 Beon-gil, Seong- san-gu, Changwon, Gyeongsangnam-do 642–120, Republic of Korea Adv. Mater. 2014, 26, 7170–7177 www.advmat.de www.MaterialsViews.com