IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 12, NO. 1, JANUARY 2004 67 Substrate Coupling in Digital Circuits in Mixed-Signal Smart-Power Systems Radu M. Secareanu, Scott Warner, Scott Seabridge, Cathie Burke, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Ivan S. Kourtev, Member, IEEE, and Eby G. Friedman, Fellow, IEEE Abstract—This paper describes theoretical and experimental data characterizing the sensitivity of nMOS and CMOS digital circuits to substrate coupling in mixed-signal, smart-power systems. The work presented here focuses on the noise effects created by high-power analog circuits and affecting sensitive digital circuits on the same integrated circuit. The sources and mechanism of the noise behavior of such digital circuits are identified and analyzed. The results are obtained primarily from a set of dedicated test circuits specifically designed, fabricated, and evaluated for this work. The conclusions drawn from the theoretical and experimental analyses are used to develop physical and circuit design techniques to mitigate the substrate noise problems. These results provide insight into the noise immunity of digital circuits with respect to substrate coupling. Index Terms—Noise, smart-power, substrate coupling. I. INTRODUCTION S UBSTRATE noise can affect the proper operation of both analog and digital integrated circuits. Substrate noise in cer- tain analog applications has received a great deal of attention during the past decade particularly because of the requirements for high-resolution analog and RF signal processing [1]–[6]. A variety of techniques to decrease the effects of noise these sensitive analog circuits—technological, physical, circuit, and others—have been proposed and studied. These techniques in- clude choices for the manufacturing technology, the substrate thickness and doping concentrations, the physical separation be- tween noise aggressors and victims, the placement of substrate contacts, guard rings, and wells, the use of a backplane sub- strate contacts/biasing, signals transition times, and routing of the power lines [1]–[6]. Additional aspects of the substrate noise mitigation problem are represented by models of the substrate and integrating these models into existing simulation tools and design methodologies [7]–[15]. The substrate noise immunity of digital circuits, however, has received far less attention. One particular reason is that because of the natural noise rejection capabilities—that is, the Manuscript received January 31, 2002; revised August 20, 2002. This work was supported in part by a Grant from the Xerox Corporation. R. M. Secareanu is with Motorola, Inc., SPS/Digital DNA Laboratories, Tempe, AZ 85284 USA. S. Warner, S. Seabridge, C. Burke, J. Becerra, T. E. Watrobski, C. Morton, W. Staub, and T. Tellier are with Xerox Corporation, Ink Jet Supplies Business Unit, Webster, NY 14580 USA. I. S. Kourtev is with the Department of Electrical Engineering, University of Pittsburgh, Pittsburgh, PA 15261 USA (e-mail: ivan@engr.pitt.edu). E. G. Friedman is with the University of Rochester, Department of Electrical and Computer Engineering, Rochester, NY 14627 USA. Digital Object Identifier 10.1109/TVLSI.2003.820526 existence of an inherent noise margin—digital circuits tolerate a relatively higher amount of noise as compared to analog circuits. Furthermore, substrate noise adversely affects digital circuits only in a limited class of applications where sufficiently strong on-chip substrate noise levels are not unusual. Smart-power on-chip systems with high-power analog drivers represent one such application. Regardless of the particular noise source—an analog or a dig- ital circuit—substrate noise problems are typically mitigated by employing technological features providing a high degree of component isolation, or by avoiding the integration of dig- ital and analog components on the same chip substrate (e.g., by using multichip modules). Both of these approaches, however, significantly increase the cost of the final product. Furthermore, substrate noise problems are expected to dete- riorate in future generations of deep submicrometer (DSM) sys- tems requiring on-chip integration of complex digital and analog circuits. From the digital circuits perspective, the lower power supply voltage of these systems exacerbates the problems as the digital noise margins decrease [16]. In systems-on-a-chip (SoC), for example, complex digital processing and control circuitry are integrated on the same integrated circuit (IC) with sensitive analog processing blocks, RF circuits, and high-power circuitry. Since SoCs are typically implemented in a standard digital process—the reasons being enhanced process control and lower cost—reliable solutions are required to achieve minimal noise interaction amongst the various on-chip circuit components. Considering the stringent system performance requirements in ultra-scaled DSM systems [16], the noise immunity of digital circuits to substrate noise becomes increasingly important. This paper focuses on the noise behavior of digital circuits in mixed-signal systems. The work presented here considers mul- tiple issues related to substrate noise as follows: 1) determining the mechanisms of substrate noise transmis- sion and behavior within digital circuits; 2) comparing the theoretical and experimental noise be- havior of digital circuits; 3) providing circuit and physical design techniques to im- prove the noise reliability of both digital and analog com- ponents of a SoC. The rest of this paper is organized as follows. The noise be- havior of digital circuits is discussed in Section II. Test circuits and the experimental results from evaluating these circuits are presented in Section III. Substrate contact placement to mini- mize the adverse effects of substrate noise on both the analog and digital components of an SoC is discussed in Section IV, 1063-8210/04$20.00 © 2004 IEEE