Huang et al. / J Zhejiang Univ Sci A 2009 10(2):151-164 151 Gradual refinement for application-specific MPSoC design from Simulink model to RTL implementation # Kai HUANG †1 , Xiao-lang YAN 1 , Sang-il HAN 2 , Soo-ik CHAE 2 , Ahmed A. JERRAYA 3 , Katalin POPOVICI 4 , Xavier GUERIN 4 , Lisane BRISOLARA 5 , Luigi CARRO 5 ( 1 Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China) ( 2 System Design Group, Seoul National University, Seoul 151-744, Korea) ( 3 CEA-LETI, Grenoble 38054, France) ( 4 SLS Group, TIMA Laboratory, Grenoble 38031, France) ( 5 Informatics Institute, Federal University of Rio Grande do Sul, Porto Alegre 15064, Brazil) † E-mail: huangk@vlsi.zju.edu.cn Received Jan. 28, 2008; Revision accepted July 30, 2008; Crosschecked Oct. 28, 2008 Abstract: The application-specific multiprocessor system-on-chip (MPSoC) architecture is becoming an attractive solution to deal with increasingly complex embedded applications, which require both high performance and flexible programmability. As an effective method for MPSoC development, we present a gradual refinement flow starting from a high-level Simulink model to a synthesizable and executable hardware and software specification. The proposed methodology consists of five different abstract levels: Simulink combined algorithm and architecture model (CAAM), virtual architecture (VA), transactional accurate archi- tecture (TA), virtual prototype (VP) and field-programmable gate array (FPGA) emulation. Experimental results of Motion-JPEG and H.264 show that the proposed gradual refinement flow can generate various MPSoC architectures from an original Simulink model, allowing processor, communication and tasks design space exploration. Key words: Multiprocessor system-on-chip (MPSoC) design, Refinement, Simulink, SystemC, Motion-JPEG, H.264 doi:10.1631/jzus.A0820085 Document code: A CLC number: TN402; TP36 INTRODUCTION With the increasing demand for complex em- bedded applications, heterogeneous multithreaded multiprocessor system-on-chip (MPSoC) architec- tures are becoming attractive solutions, because of their high computation power and flexible program- mability (Jerraya et al., 2005). MPSoC hardware architectures may be represented, without loss of generality, as a set of processing nodes or components which interact via a communication network (Jerraya et al., 2006). As shown by (a) in Fig.1, processing nodes may be either hardware or software. Software nodes are those programmable sub-systems with one or several processors. The heterogeneity of proces- sors implies the need for multiple software stacks that may require different computation and communica- tion performances. The MPSoC software stack is organized by three layers: application software, hardware dependent software (HdS), and hardware abstraction layer (HAL) (Jerraya et al., 2006), as shown by (b) in Fig.1. The application software may be a multithreaded description of the application, which makes use of high-level primitives (HdS API) to abstract the underlying platform. The HdS consists of a thread library and a specific I/O communication library. The HAL is responsible for architecture- specific services (HAL API), such as context switching, interrupt service routines, specific hard- ware components, and specific I/O controls. As more Journal of Zhejiang University SCIENCE A ISSN 1673-565X (Print); ISSN 1862-1775 (Online) www.zju.edu.cn/jzus; www.springerlink.com E-mail: jzus@zju.edu.cn # Expanded based on “Simulink-based MPSoC Design Flow: Case Study for Motion-JPEG and H.264” by Kai Huang, Sang-il Han, et al., which appeared in the Proceedings of the 2007 Design Automa- tion Conference (DAC 2007)