Development and Evaluation of Lead Free Reflow Soldering Techniques for the Flip Chip Bonding of Large GaAs Pixel Detectors on Si Readout Chip M. Klein, M. Hutter, H. Oppermann, T. Fritzsch, G. Engelmann, L. Dietrich, J. Wolf, B. Brämer, R. Dudek, H. Reichl* Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration / *TU-Berlin Gustav-Meyer Allee 25, Germany-13355 Berlin Email: klein@izm.fhg.de, phone : +49 30 46403-612 Abstract Lead free reflow soldering techniques applying AuSn as well as SnAg electroplated bumps were chosen for the evaluation of the flip chip bonding process for a x-ray pixel detector. Both can be used in pick & place processes with a subsequent batch reflow suitable for high volume production. AuSn solder was selected due to its fluxless bondability, the good wettability and the self-alignment process capability and SnAg solder due to its more ductile behaviour and lower yield stress compared to AuSn. GaAs test chips with daisy chain and four point Kelvin probe structures together with appropriate Si test substrates were designed, manufactured and bumped. Test chips with 55 and 170 µm pitch and different chip sizes (maximum 16.3 down to 4 mm square) were used. AuSn bumps were deposited by electroplating Au first and Sn on top. Au bumps were also formed on substrate side. Two under bump metallizations (UBM) were used for the SnAg samples: Cu and Ni. FE simulation was performed for AuSn and SnAg interconnections and for different chip sizes. A local model was designed for the bump interconnection and a global octant model for the whole assembly. Very high values were calculated for the peel stress using AuSn bumps. SnAg bumps on the other hand showed a 3 to 5 times reduced peel stress dependent on the chip size. A flip chip bonding process setup was carried out for both solder types, AuSn as well as SnAg, with an analysis of the samples by electrical measurements, cross sectioning and SEM. Due to the different coefficients of the thermal expansion (CTE) of GaAs and Si no stable bonding process was found for the AuSn modules as predicted by the FE analysis. With increasing chip size failures like pad lift or cracking of the GaAs were observed. The SnAg samples showed good bonding results. This technology was then selected to assemble test modules for thermal cycling between -55 and +125 °C comparing the Cu and Ni UBM. The modules were qualified by electrical monitoring as well as cross sectioning. More than 200 cycles were reached by the 55 µm pitch, 16.3 mm square, bonded GaAs chips and about 400 by the smallest, 4 mm square chips, although no underfilling was used. As failure mode a fracture within the solder was detected. Based on experimental and simulation results functional 256x256 GaAs pixel detectors with a chip size of 14x14 mm 2 were assembled on Si read out chips using SnAg bumps on a Cu UBM. Finally, these x-ray image sensors were wire bonded to a PCB and successfully tested showing a yield (on pixel-level) of about 98%. 1. Introduction Pixel detectors are in use for various applications like fundamental physics experiments or x-ray detection for medical diagnostics. Generally, hybrid pixel detectors consist of a sensor chip with an area array configuration of the pixels. Each pixel has to be connected to a readout cell of a chip for analysis and local detection of the signal. The pixel detector is flip chip bonded to the IC in order to read out each pixel diode in parallel with high repetition rate /1/. The most common flip chip bonding methods are based on evaporated or electroplated Indium bumps which are thermocompression bonded or on reflow-soldered low-melting BiPbSn. As long as pixel detector and readout chip are both made out of the same semiconductor material mechanical stress due to a mismatch of the CTEs is not an issue. This paper presents the development of a lead free solder reflow process for a x-ray image sensor which consists of a 256x256 GaAs pixel detector and a Si read out chip. AuSn as well as SnAg solder bumps can be used for fluxless bonding of the detector. However, the different mechanical behaviour of the solder materials, e.g. the yield stress at room temperature of AuSn of 275 MPa /2/ compared to SnAg of 20-30 MPa /3/, mainly influences the reliability of the bonded device. 2. Test Modules Si test substrates as well as GaAs test chips were designed and fabricated for this investigation. Different chip sizes and two different pitches, 55 and 170 µm, were realized. The contacts were arranged in an area array configuration and daisy chain as well as four point Kelvin structures were implemented. Figure 1 shows light microscopy images of substrates and assembled modules. a) b) Fig. 1: light microscopy images of (a) assembled modules and (b) substrates (selection of samples). 978-1-4244-2231-9/08/$25.00 ©2008 IEEE 1893 2008 Electronic Components and Technology Conference