A Jitter Insensitive Continuous-Time ΣΔ ΣΔ ΣΔ ΣΔ Modulator Using Transmission Lines L. Hernández 1 , P. Rombouts 2 , E. Prefasi 1 , S. Paton 1 , M. Garcia 1 , C. Lopez 1 1 Universidad Carlos III de Madrid, Madrid, Spain 2 ELIS, Ghent University, Gent, Belgium Abstract This work presents a prototype low pass continuous time sigma delta modulator which uses transmission lines in its loop filter rather than capacitive integrators. As has been shown in prior theoretical work, such a structure allows to desensitize the modulator against clock jitter and excess loop delay. The prototype single-bit modulator was designed for an oversampling ratio of 128. Clocked at 53.7 MHz it achieves a peak SNR of 67 dB. In an experiment with an excessive clock jitter of 1% of the clock period, the SNDR is degraded by only 5dB compared to the case without jitter. This is 15dB better than an equivalent modulator with capacitive integrators. 1. Introduction Continuous time sigma delta (CTSD) modulators are nowadays a proven technology for high speed A/D converter implementation [1]. However, CTSD modulators are more sensitive to circuit impairments than switched capacitor implementations. Some of the performance limiting factors of CTSD modulators are clock jitter and excess loop delay [1], [2], [3]. In [4] a delay linear system is proposed to implement the loop filter of a CTSD modulator. This linear system may process a sequence of pulses, such as the feedback DAC signal of the modulator, into another sequence of similar pulses. This property is used in [5] to desensitize the CTSD modulator from jitter and excess loop delay. In this work, we present a CMOS implementation of the modulator proposed in [5]. In this proof-of-concept single-bit modulator, off-chip transmission lines are used to implement the delays. A future design could employ on-chip resonators, such as integrated transmission lines or MEMS devices. The presented work describes the circuit design and the measurements that demonstrate the usefulness of the overall concept. 2. CTSD modulators with transmission lines Figure 1 shows the system level diagram of the CTSD modulator with transmission lines [5]. The blocks named H implement the following transfer function: () sT sT e e s H - - - + = 1 1 (1) This transfer function is proportional to the impedance of an open circuit transmission line, where T corresponds to the delay of the transmission line. If this delay T is equal to the period of the sampling clock, this diagram can be used to implement a CTSD modulator that has nearly identical properties as a discrete time counterpart [5]. This way a modulator with a large insensitivity toward jitter and excess loop delay is obtained. In this work, d i coefficients are chosen such that the CTSD modulator is equivalent to the ideal second-order lowpass discrete time modulator. Mathematically this can be written as: ( ) ( ) ( ) ( ) () ( ) ( ) ( ) 1 3 1 1 2 1 3 2 3 2 1 1 1 , 1 - - - - + + + = - = = - = - d d d H d d d H d e s NTF z z NTF s NTF z NTF sT sT e z (2) This yields the values d 1 =1 , d 2 =3 , d 3 =1/4. Coefficient d 3 may be neglected in our single-bit design. Figure 1. System level diagram of a 2nd order modulator implemented with transmission lines. Now we will focus on the circuit implementation of fig. 1 using transmission lines. A circuit that exactly mimics the behavior of the system of figure 1 is shown in figure 2 [5]. It is implemented with transmission lines, transconductors and a current feedback DAC. v(t) λ/4 gm1= 1/Zo ZL open R1=ZO λ/4 gm2= 1/Zo ZL open R2=3ZO fs=1/T y[n] Ir -Ir z -1 v1(t) v2(t) Figure 2. Conceptual circuit implementation of a CTSD modulator with transmission lines. The combination of a transconductor and the transmission line produces the same transfer function as blocks H in fig. 1. The previously defined d i coefficients, are implemented by adding series resistors to the transmission lines. The appropriate values of these resistors and the transconductors are expressed in Table I. Here fs corresponds to the sampling frequency, Z 0 to x(t) d3 H + y(n) fs=1/Ts + + H d 1 d2 z -1 109 0-7803-8715-5/04/$20.00 ©2004 IEEE.