Analysis and optimization of dynamically reconfigurable regenerative comparators for ultra-low power 6-bit TC-ADCs in 90 nm CMOS technologies Juan A. Montiel-Nelson n , Víctor Navarro, Javier Sosa, Tomás Bautista Institute for Applied Microelectronics, University of Las Palmas de Gran Canaria, 35017 Las Palmas de Gran Canaria, Spain article info Article history: Received 15 February 2013 Received in revised form 6 November 2013 Accepted 6 February 2014 Keywords: Threshold configuring ADC Ultra-low power analog-to-digital converters Reconfigurable analog circuits Regenerative comparators FTL comparators Low power analog design abstract In this paper, the optimization and analysis of threshold configurable regenerative comparators (TC) for use in ultra-low power consumption ADCs is introduced (TC-ADC). Using a 90 nm CMOS technology, the obtained comparator achieves a 77% improvement in terms of power consumption ð3 μWÞ when compared with previously published TC comparators, while maintains the same full scale specification ( 7160 mv). The proposed design exhibits a delay time of 1.31ns — a 20% of improvement — which allows achieving for a 6-bit TC-ADC up to 25 MS/s for a sampling period of 40 ns. Furthermore, offset, gain and non-linearity errors of a 6-bit TC-ADC is also analyzed for both perfectly matched devices and under the presence of manufacturing dependent device mismatch scenarios. The higher energy efficiency of the optimized comparator increases the linearity of the TC-ADC by a 50% in offset, gain, DNL and INL. Although, a mismatch analysis of 30 MonteCarlo simulations and 3s device parameter variations exhibits a higher non-linearity for the threshold comparators, the gain, offset and DNL errors for the optimized one are diminished in a 37%,12% and 17%, respectively. & 2014 Elsevier Ltd. All rights reserved. 1. Introduction Last two decades of evolution in microelectronics technologies have allowed a dramatic change and sophistication of digital signal processing systems. Mixed signal integrated circuits and systems — including data conversion and acquisition — have contributed greatly to those changes, such as nowadays a wide diversity of continuous-time signals are operated efficiently by digital and analog devices. In particular, powerful processors have been developed for mixed signal processing, allowing for longer word- length, higher operation frequencies and larger memory sizes. At the data conversion side, most of the research effort was aimed for increasing the sampling rate and the resolution of the analog- to-digital and digital-to-analog converters to meet real-time multimedia processing requirements. In the literature, several acquisition methodologies and archi- tectures were presented to support a wide range of applications oriented to process huge volume of data [1]. Nowadays, several emerging applications for collecting and processing analog data are subject to strong energy consumption restrictions, e.g. mobile phones containing gyroscopes and accelerometers among other sensors assisting Global Positioning System (GPS) for navigation applications; sensor networks supported by small batteries, or medical aids using remote sensing battery-less are typical ultra- low power applications requiring ADC subsystems. For those before mentioned applications, specifications related to both conversion rate and resolution are less restrictive than the power consumption requirements. Usually, when a few samples or kilo- samples per second of 4–8 bit resolutions are demanded then ultra- low power requirements are satisfied. Successive approximation register (SAR) and ΣΔ converters are suitable architectures [2] for this purpose. From all ADC architectures in the literature, SAR figure of merits — performance comparisons in terms of area and power consumption — is better against other topologies [3,4], when a medium and low conversion rate (1–500 MS/s) is demanded. As high performance technologies are mainly focused on reducing the delay while maintaining low power consumption in the digital circuitry, an increment of the digital section in comparison with the analog one is more effective in ADC design [5]. In this sense, several approaches have been presented on how to optimize the digital controller reducing the power and increasing the conversion speed on SAR ADC architectures by using compara- tor-based binary search [6,7] and asynchronous controllers [8–10]. In a comparator-based asynchronous binary search ADC (CABS), the need of digital-to-analog conversion and digital controller is Contents lists available at ScienceDirect journal homepage: www.elsevier.com/locate/mejo Microelectronics Journal http://dx.doi.org/10.1016/j.mejo.2014.02.005 0026-2692 & 2014 Elsevier Ltd. All rights reserved. n Corresponding author. Tel.: þ34 928 451 252; fax: þ34 928 451 083. E-mail address: montiel@iuma.ulpgc.es (J.A. Montiel-Nelson). Please cite this article as: J.A. Montiel-Nelson, et al., Analysis and optimization of dynamically reconfigurable regenerative comparators for ultra-low power 6-bit TC-ADCs in 90 nm CMOS technologies, Microelectron. J (2014), http://dx.doi.org/10.1016/j.mejo.2014.02.005i Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎