Understanding the potential and limitations of HfAlO as interpoly dielectric in floating-gate Flash memory B. Govoreanu * , R. Degraeve, M.B. Zahid, L. Nyns, M. Cho, B. Kaczer, M. Jurczak, J.A. Kittl, J. Van Houdt IMEC, Kapeldreef 75, B-3001 Leuven, Belgium article info Article history: Received 3 March 2009 Received in revised form 11 March 2009 Accepted 11 March 2009 Available online 18 March 2009 Keywords: HfAlO High-k materials Defect density Interpoly dielectrics Flash memory NAND abstract Introduction of high-k dielectrics in Flash memory is seen as a must for the upcoming technology nodes. Hafnium aluminate (HfAlO) has been identified as a possible candidate for implementing the interpoly dielectric in floating gate memory. In this work, we establish a link between the material morphology and its electrical response, allowing to understand memory device behavior and to consequently assess the potential and limitations of HfAlO as IPD in a memory cell. Ó 2009 Elsevier B.V. All rights reserved. 1. Introduction Aggressive shrinking of the floating gate memory cell for future NAND technology nodes may require planarization, which leads to the loss of the sidewall coupling capacitance. Its restoration re- quires considerable reduction of the electrical thickness of the interpoly dielectric (IPD) [1,2]. This cannot be achieved with to- day’s oxide–nitride–oxide (ONO) IPDs, scalability of which is lim- ited to about 10 nm electrical thickness (EOT) [3]. Consequently, introduction of high-k materials as IPDs is the immediate option. However, these materials are known to have a rather high defect density, which may hinder the success of this approach. Hafnium aluminate (HfAlO) has been identified as a potential candidate. Triple-layer SiO 2 /HfAlO/SiO 2 blocking dielectric stacks have been demonstrated in Si-nanocrystal memory [4]; this ap- proach allows some scalability gain over ONO, however, limited by the presence of the bottom and top SiO 2 layers. Aggressively scaled HfAlO-based IPDs, of <5 nm EOT, were also demonstrated in a planar floating gate structure [5]. In spite of promising results, targeting an IPD for next generation multilevel cell NAND Flash re- quires (at least) combining a large program window, which needs to be achievable at operating voltages, with good retention. With a planar architecture constraint, these requirements impose reduc- tion (ideally, to suppression) of the bottom SiO 2 layer in a high-k IPD stack [5], combined with a suitable electrical and physical thickness of the IPD and low(-enough) high-k defect density. In this work, we summarize the results of a comprehensive investigation of HfAlO, where the targeted EOT is in the range of 5–8 nm. A dual-stance approach, from both material and electrical perspectives, is taken, with the ultimate goal of understanding de- vice behavior and consequently being able to assess the potential and limitations of HfAlO as IPD in floating-gate Flash memory. 2. Dielectric deposition and test samples HfAlO layers of different compositions have been deposited using Atomic Layer Deposition (ALD) by alternating deposition cy- cles for Al 2 O 3 (from Al(CH 3 ) 3 and H 2 O precursors) and HfO 2 (HfCl 4 and H 2 O precursors) in a 300 mm ALD reactor. Different Al 2 O 3 :H- fO 2 deposition cycle ratios ranging from 1:3 to 3:1 were consid- ered, yielding a corresponding Hf-content (relative to Al) between 15% and 64%. A 1:1 deposition cycle ratio (1:1cy) resulted in about 37% Hf-content. Blanket wafers, capacitors/transistors as well as planar memory structures [5] with a 8.5 nm tunnel oxide and HfAlO-based IPDs were used in order to characterize the mate- rial physically and electrically. 3. Results A linear dependence of the dielectric constant on the composi- tion was found, while internal photoemission and photoconductiv- ity experiments revealed that samples of all compositions, 0167-9317/$ - see front matter Ó 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2009.03.099 * Corresponding author. Tel.: +32 16 281337; fax: +32 16 381844. E-mail address: bogdan.govoreanu@imec.be (B. Govoreanu). Microelectronic Engineering 86 (2009) 1807–1811 Contents lists available at ScienceDirect Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee