Fault detection in CMOS/SOI mixed-signal circuits using the quiescent current test D. De Venuto a, * , M. Kayal b , M.J. Ohletz c a Dipartimento di Elettrotecnica ed Elettronica, Politecnico di Bari, via Orabona 4, 70125 Bari, Italy b LEG, Ecole Polytechnique Federal de LausanneÐEcublens, Lausanne, Switzerland c Alcatel Microelectronics, Excelsiorlaan 44-46, 1930 Zaventem, Belgium Received 20 June 2001; revised 16 January 2002; accepted 21 January 2002 Abstract Main stream bulk CMOS and the variants of silicon-on-insulator SOI) CMOS technologies are discussed with respect to testing for the quiescent current of mixed-signal integrated SOI circuits. The 2±3 times lower static power consumption in fully depleted CMOS/SOI compared to bulk CMOS allows quiescent current testing also for high performance analogue circuits at an acceptable defect resolutions. From ®rst simulations and technological considerations, it turned out that quiescent current tests are able to detect not only commonly known defects, but also SOI speci®c defects such as self-heating, kink-effect or the parasitic bipolar behaviour. It is further shown that in partially depleted thick-®lm SOI, the kink-effect and parasitic bipolar transistor support the quiescent current test for some speci®c defects as they elevate the defective quiescent current level. In fully depleted kink-free SOI circuits, the kink-effect may occur due to process failures but then can be detected by quiescent current tests. A special fault simulation model for the kink-effect is presented. The I ccq test technique is studied for a CMOS/SOI Miller operational ampli®er. Normal 6-s variation of the aspect ratio and the threshold voltage do not jeopardise the defect detection in the quiescent current. First, results con®rm the good detection capabilities of the quiescent current test, in particular, of failures which are not visible in the output voltage. q 2002 Elsevier Science Ltd. All rights reserved. Keywords: Quiescent current; Test; I ddq ; I ccq ; Silicon-on-insulator; Kink-effect; Sub-threshold current; Defects; Fault simulation model 1. Introduction For almost two decades I ddq testing is now in practical use as a rapid and, thus, low cost test technique for digital CMOS circuits. The simple and well-known principle is based upon the fact that in the idle mode only a very low leakage current is ¯owing between the supply and the ground terminal, since in this mode no low ohmic path exists. Moreover, this is true for all idle modes of a digital CMOS circuit, i.e. for different input patterns or states of a sequential. This allows the testing of the digital circuit in different idle states. Due to this, any defect causing a current consumption signi®cantly higher than this idle or quiescent current I ddq can be detected. Typical quiescent currents are in the range of 10s of nA, whereas circuits with a defect are in the range of mA or even mA. This results in a good defect detection resolution and defective circuits can be easily and reliably distinguished from good circuits. Thus, this method has a low yield loss and a low test escape rate. This is true since there is no overlapping range between the assumed) normal distribution of the quiescent currents for good and defective circuits. However, there are two cases where this test technique reaches its limits. For digital circuits, the move to deep sub- micron technologies e.g. 0.13 mm) constitutes such a limitation for the application of I ddq . For such technologies the distribution of the parasitic and the leakage current, mainly the sub-threshold currents, can overlap with the distribution of quiescent currents of a defective device. In consequence of a reliable discrimination between good and defectivedevicesatanacceptableyieldloss/testescapetrade- off is not possible. Either the test yield loss is too high, or the test escapes are compromising the outgoing quality. The second restriction applies to mixed-signal circuits that have become a very important semiconductor market. Unfortunately, I ddq testing cannot be used for the analogue part to the same extent as for the digital counterpart since the stand-by or quiescent current consumption of analogue circuits is some order of magnitudes higher than that of pure Microelectronics Journal 33 2002) 387±397 Microelectronics Journal 0026-2692/02/$ - see front matter q 2002 Elsevier Science Ltd. All rights reserved. PII: S0026-269202)00008-3 www.elsevier.com/locate/mejo * Corresponding author. E-mail addresses: d.devenuto@poliba.it D. De Venuto), maher.kayal@ep¯.ch M. Kayal), michael.ohletz@mie.alcatel.be M.J. Ohletz).