Testing of Analogue Circuits via (Standard) Digital Gates D. De Venuto DEE- Politecnico di Bari, Italy, d.devenuto@poliba.it M. J. Ohletz Alcatel Microelectronics,Belgium michael.ohletz@mie.alcatel.be B. Riccò DEIS Università di Bologna bricco@deis.unibo.it Abstract The possibility of using window comparators for on- chip (and potentially on-line) response evaluation of analogue circuits is investigated. No additional analogue test inputs are required and the additional circuitry can be realised either by means of standard digital gates taken from an available library or by full custom designed gates to obtain an observation window tailored to the application. With this approach, the test overhead can be kept extremely low. Due to the low gate capacitance also the load on the observed nodes is very low. Simulation results for some examples show that 100% of all assumed layout-realistic faults could be detected. 1. Introduction Out-going quality is one of the key issues in highly reliable applications like automotive, public transportation or aerospace applications. Besides the process quality cost-effective testing is one of the parameters to achieve high quality. The most cost-effective way of testing in terms of test time optimization and also time-to-market is Design-for-Testability (DfT). Today a wide range of DfT techniques exists for digital integrated circuits (IC), but only a few proposals are known for mixed-signal ICs. Since test costs can always be traded off against die area, DfT also becomes interesting for cost sensitive products like consumer or automotive mixed-signal ICs. For those products an interesting test solution which can be easily accommodated in the production test program, consists in checking whether or not certain DC-operating points or signal levels on critical circuit nodes are within their design limits. This check can be performed at different (test) time instances, supply voltage conditions and temperatures. Furthermore, the continuous observation of critical nodes can also be used during the application to achieve on-line self-checking capabilities (similar like for digital ICs) [1] e.g. to flag failures to a control unit in safety-critical applications. This paper deals with a cost- effective method for such an on-chip evaluation/observation of signal levels. It only requires a digital window comparator that can be area effectively implemented by merely digital logic gates. 2. Previous work In order to check the correctness of analogue voltages at (selected) nodes to be observed, analogue comparators have been proposed and a few are briefly summarised. In [2] a strobed comparator with a variable threshold is described, that can be used as a waveform digitizer. This solution, however, demands high requirements in terms of bandwidth and clock skew/jitter. Another, very specific application of on-chip analogue differential comparator [3] is used to measure the dynamic performance of the differential sense amplifier of SRAMs and to compare it with an externally applied differential signal. A bias- programmable, clocked two-mode comparator with hysteresis for mixed-signal ICs is introduced in [4]. In this approach the analogue comparator is implemented by a functional conversion of system OTAs or operational amplifiers (OpAmp) during test mode [5], in which different thresholds can be programmed via the biasing from the digital part. However, all these solutions require careful analogue design, have significant area occupation and, possibly, need critical reference voltages. Finally, digital window comparators have been already outlined in [6]. Unlike the above proposals, the simple solution proposed here, is based on digital gates that require minimal or no additional silicon area and does not require any reference voltage. Such a solution is of particular interest for mixed- signal ICs, where digital gates are already available from standard libraries. On the other hand, the scheme of this work can also be implemented with dedicated logic gates featuring non-standard logical switching thresholds. Such Proceedings of the International Symposium on Quality Electronic Design (ISQED02) 0-7695-1561-4/02 $17.00 ' 2002 IEEE