150 IEEE TRANSACTIONS ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, VOL. 1, NO. 2, JUNE 2011 Modeling of Layout Aware Line-Edge Roughness and Poly Optimization for Leakage Minimization Yongchan Ban, Student Member, IEEE, and David Z. Pan, Senior Member, IEEE Abstract—Line-edge roughness (LER) highly affects the device saturation current and leakage current, which leads to serious de- vice performance degradation. In this paper, we propose the first layout-aware LER model where LER is highly related to the litho- graphic aerial image fidelity and neighboring geometric proximity. With our new LER model, we perform robust LER aware poly layout optimization to minimize the degradation of device perfor- mance, in particular leakage current. The results on 32-nm node standard cells show average 91.26% reduction of leakage current and 4.46% improvement of saturation current at the worst case process corner despite 8.86% area penalty. Index Terms—Design for manufacturing, layout optimization, leakage, line-edge roughness (LER), lithographic variation, VLSI design. I. INTRODUCTION A S SEMICONDUCTOR device nodes continue to shrink down to 32 nm and below, the complexity of designs is significantly increasing due to process variation. Among sources of process variation, lithographic printability variation is one of the most fundamental challenges because it directly impacts on yield and performance. Despite of advances in resolution-enhancement techniques (RET) such as optical proximity correction (OPC), phase-shifting mask (PSM), off-axis illumination (OAI), etc., lithographic variation still continues to be a challenge [1]. Two types of lithography variations which result in undesirable performance mismatch in identically designed transistor are: 1) systematic lithography variation and 2) random lithography variation. The systematic lithography variation is introduced due to de- terministic pattern proximity by the limitation of the lithography equipment where 193-nm wavelength are still used even for sub-32-nm technology nodes. Layout geometries such as neigh- boring gates, convex and concave corners, jogs, and line-ends result in the systematic variation. To address the problem of systematic lithography variation from a design perspective, sev- Manuscript received December 29, 2010; revised May 11, 2011; accepted May 16, 2011. Date of publication June 27, 2011; date of current version Au- gust 19, 2011. This work is supported in part by the National Science Foundation (NSF) under CAREER award, in part by the Semiconductor Research Corpo- ration (SRC), and equipment donations from Intel Corporation. This paper was recommended by Guest Editor E. Macii. The authors are with the Department of Electrical and Computer Engineering, University of Texas, Austin, TX 78712 USA (e-mail: ycban@utexas.edu; dpan@ece.utexas.edu). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JETCAS.2011.2159286 eral authors have proposed lithography-aware characterization methods [2]–[4]. In [2], the authors proposed a gate slicing and effective gate length (EGL) method to calculate the impact of nonrectangular gate shapes. Another work [3] proposed a mod- eling card to combine different EGLs from look-up tables of driving current and leakage current. The second type of lithography variation is caused by random uncertainties in the fabrication process such as line-edge rough- ness (LER). At the same time, many nonlithographic sources of variation such as dopant variation [5], [6] and gate dielectric thickness variation [7], [8] are also the result of aggres- sive scaling. Among them, LER was regarded as a small fraction of the statistical variability in the past since the critical dimen- sions (CD) of MOSFET was much larger than LER. However, as the aggressive scaling continues into the nanometer regime, LER does not scale accordingly and becomes an increasingly larger fraction of the gate length [9], [10]. For channel lengths above 32 nm the random dopants are the dominant source of fluctuations, but below this channel length LER takes over and becomes a major fluctuation source [7]. Thus it can be one of the performance limiting components for technologies 32 nm and below. LER is mainly caused by erosion of polymer aggregates at the edge of photo-resist (PR) during development process [11]. To address LER impact, many works have been proposed in a sim- ulation manner [12]–[15]. The work of [6] and [16] presented the impact of LER on the variation of threshold voltage with statistical timing analysis. Even if many works on LER mod- eling have been performed, these works have been focusing on process level and unit device level simulation. According to our experiments, LER is highly related to lithography image fidelity which is mainly driven by lithography process and layout prox- imity. Since each device in a cell might have different LER due to different layout proximity, there is great demand to study on a cell level LER model which considers neighboring pattern prox- imity due to lithography to analyze the impact of LER on circuit performance, in particular leakage current. Standard cells are pervasively used in digital designs as basic circuit blocks. Since a large amount of identical cells will be used repeatedly, any small changes to reduce gate length vari- ation in standard cells can result in significant improvements at the design level [17]. There are a lot of layout patterns in a standard cell, and each pattern may have a different patterning fidelity and different LER impact. Thus a new LER model con- sidering both aerial image fidelity and neighboring pattern prox- imity is required. In this paper, we propose a LER-aware layout optimization to minimize leakage current in a cell. Our approach is mainly based 2156-3357/$26.00 © 2011 IEEE