TROY: Track Router with Yield-driven Wire Planning Minsik Cho, Hua Xiang ∗ , Ruchir Puri ∗ , David Z. Pan ECE Dept. Univ. of Texas at Austin, Austin, TX 78712 ∗ IBM T. J. Watson Research Center, Yorktown Heights, NY10598 thyeros@cerc.utexas.edu, huaxiang@us.ibm.com, ruchir@us.ibm.com, dpan@ece.utexas.edu ABSTRACT In this paper, we propose TROY, the first track router with yield-driven wire planning to optimize yield loss due to ran- dom defects. As the probability of failure (POF ) com- puted from critical area analysis and defect size distribu- tion strongly depends on wire ordering, sizing, and spacing, track routing plays a key role in effective wire planning for yield optimization. TROY formulates wire ordering into a preference-aware minimum Hamiltonian path problem. For simultaneous wire sizing and spacing optimization, TROY solves it optimally by formulating the problems into a sec- ond order conic programming (SOCP). Experimental results show that TROY can reduce the random-defect yield loss by 18% on average without any overhead in wirelength, com- pared with the widely used greedy approach. Categories and Subject Descriptors B.7.2 [Hardware, Integrated Circuit]: Design Aids General Terms Algorithms, Design, Performance Keywords VLSI, Track Routing, Yield, Manufacturability 1. INTRODUCTION Smaller feature size makes nanometer VLSI designs vulnerable to ever-growing yield loss due to both random and systematic causes [17]. While it is believed that the yield loss due to system- atic sources is greater than that due to random defects during the technology and process ramp-up stage, the systematic yield loss can be largely eliminated when the process becomes ma- ture and systematic variations are extracted/compensated. On the other hand, the random defects which are inherent due to manufacturing limitations will still be there even for mature fab- rication process [17]. Thus, its relative importance will indeed be much bigger for mature process with systematic variations designed in. Among random defects, the density of back-end- of-line (BEOL) defects (i.e., interconnect defects) is increasing, compared to that of front-end-of-line (FEOL) defects (i.e., de- vice defects) [16]. Since the random BEOL defects mainly occur either between physically adjacent interconnects (short defects) or on interconnect itself (open defects), routing and interconnect optimization should be the suitable stage for random-defect yield optimization [4, 17, 21]. This work is supported in part by SRC, IBM Faculty Award, Fujitsu, and equipment donations from Intel. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. DAC 2007, June 4–8, 2007, San Diego, California, USA. Copyright 2007 ACM ACM 978-1-59593-627-1/07/0006 ...$5.00. In general, routing consists of two steps, global routing and de- tailed routing. Global routing plans an approximate path for each net, while detailed routing finalizes the exact DRC-compatible pin-to-pin connections. Track routing, as an intermediate step between global and detailed routing, can expedite detailed rout- ing by embedding major trunks from each net within a panel (a row/column of global routing cells) in DRC-friendly manner [3]. Such track routing is an appealing stage to optimize critical area for yield enhancement, as decent flexibility in routing optimiza- tion exists with wire adjacency information [8,17,26], while global routing is lack of wire adjacency information for accurate criti- cal area estimation and detailed routing cannot provide enough flexibility for significant yield improvement. Due to the criticality of yield, there have been considerable amount of efforts to enhance yield by reducing critical area in routing or post-routing. However, there are a few drawbacks in these prior works: (a) one single defect size is considered, rather than a defect size distribution [18, 22], (b) the trade-off between open and short defects due to fixed routing area is ignored [1, 2, 16, 18, 22], (c) localized/greedy optimization is performed, which may be suboptimal [2,4,7,16,23], (d) wire adjacency information is not available for accurate critical area estimation [14,20]. In this work, we propose TROY, a track router with yield- driven wire planning (wire ordering, sizing, and spacing) to op- timize yield w.r.t random defects. TROY orders wires first to minimize overlapped wirelength between adjacent wires based on preference-aware minimum Hamiltonian path, and then performs optimal wire sizing and spacing for the ordered wires with efficient second order conic programming. As a result, globally optimal wire width and spacing as well as minimal overlapped wirelength decreases critical area, making a design robust to random defects. The major contributions of this paper include the following. • We propose TROY, a track router with yield-driven wire planning. To our best knowledge, this is the first work that yield is optimized during track routing. • We propose a simple model of probability of failure due to random defects. This simple, yet effective model enables our second order conic programming. • We show that wire ordering within a panel (the first step of wire planning in TROY) can be efficiently solved by preference-aware minimum Hamiltonian path. TROY con- siders the interaction between adjacent panels to overcome any disadvantage from isolated panel-by-panel approach. • We show that wire sizing and spacing for an entire layer (the second step of wire planning in TROY) can be formulated as second order conic programming which can be solved optimally in O(N 1.3 ). 2. PRELIMINARIES 2.1 Notations Table 1 shows a list of notations in this paper. Fig. 1 shows an example of track routing where six wires from W 1 to W 6 are assumed to be already routed (thus, p 1 to p 6 are known) within a panel P i which is bounded by T i and B i . M i is the median of x/y positions of all the pins in the panel where W i exists. If p i = M i , we can use the deviation |p i −M i | as a metric for possible wirelength increase, because the shortest trunk-steiner tree can be built with the median of pins [6]. Thus, p i should be as close as possible to M i for shorter wirelegnth and less defects.