Exploration of VLSI CAD Researches for Early Design Rule Evaluation Abstract -- Design rule has been a primary metric to link design and technology, and is likely to be considered as IC manufacturer s role for the generation due to the empirical and unsystematic in nature. Disruptive and radical changes in terms of layout style, lithography and device in the next decade require the design rule evaluation in early development stage. In this paper, we explore VLSI CAD researches for early and systematic evaluation of design rule, which will be a key technique for enhancing the competitiveness in IC market. I. Introduction For the generation of design rule (DR), there are three primary costs: process, device and layout area. All DR challenges are induced by the fabless and manufacturer s requirements to follow Moore s law. Figure 1 shows a simple schematic to explain the challenges of design rule generation. Process cost limit (PCL) represents the cost to build device structure and is determined by lithography and etching costs. The PCL is typically a lower bound in DR size axis. Device cost limit (DCL) is the cost to satisfy device performance target. Area cost limit (ACL) depends on the cost for Logic/SRAM cell dimension and determines the upper bound of DR size. Design rule is determined by the three common windows. As the scaling goes into nanometer regime, the common window gets smaller. Several efforts to put DRs into the common window include double patterning lithography (DPL) for process cost [1-2], strain-driven performance boosting for device cost, local interconnect and regular layout style for area cost [3]. Figure 1. Simple schematic of three primary costs. In this paper, we explore the VLSI CAD researches to develop design rule and introduce frameworks to assess the design rule in terms of process, device and area metrics. Research directions will be discussed with examples in following sections. II. VLSI CAD Researches A. Process (lithography) evaluation Figure 2. Lithography workflow framework. Due to the growing number of tool, material and process changes required at each successive technology generation, exploration of optimum design rules for a technology node is an increasingly complicated and time consuming activity. Many good modeling tools are available for process and layout predictions. However, generally these modeling tools are designed to work as a point tool for individual optimization of a process or sub-process, they are not designed to connect to a range of other point tools. For an optimization activity as complex as design rule exploration, better integrated flow and analysis methods are required in order to reduce the high time and effort needed to be successful with point tools. We propose the lithography workflow framework in Figure 2. (a) Relaxed design rule (b) Aggressive design rule Figure 3. DPL aware design rule. DPL is the only choice for sub-20nm patterning, which causes a new interaction between router and design rule. There are two approaches to enhance decomposability for the metal DPL. The first approach is to enforce router decomposable by using relaxed design rule. We can avoid patterns that generate native conflicts by relaxed Tip-Tip-Side rule as shown in Figure 3 (a), which can make sure to remove indecomposable odd-cycle patterns [4]. However, since relaxed DR increases overall chip area, we need to be careful to define DR for DPL friendly layout. More aggressively, we can use non-relaxed Lithography Workflow Framework Layout/ Design Style Point Tool #1 Point Tool #2 : : Point Tool #n Analysis Support Cost-effective Optimum Design Rule Chul-Hong Park, David Z. Pan * and Kevin Lucas + CAE, Semiconductor R&D center, Samsung Electronics * ECE Department, University of Texas at Austin + Silicon Engineering Group, Synopsys Inc. chul.h.park@samsung.com , dpan@ece.utexa.edu , kevin.lucas@synopsys.com 978-1-4244-7516-2/11/$26.00 ©2011 IEEE 4D-4 405