Concurrent Analysis of Signal-Power Integrity and EMC for High-Speed Signaling Systems Edward K. Chan, Mauro Lai, Myoung Joon Choi, Woong Hwan Ryu Intel Corporation, USA Email: edward.k.chan@intel.com Abstract— A robust co-analysis approach for signal integrity, power integrity, and electromagnetic compatibility is successfully established and demonstrated through the investigation of several signal referencing configurations in Double Data Rate (DDR) memory systems. The characterization of power noise coupling into signal channels for two configurations is presented. In addition, a new metric that quantifies the entire signaling system combining simultaneous switching noise and crosstalk is detailed. Finally, the radiated emissions from the power planes in the signalling system are reduced through the proper placement of decoupling capacitors. Keywords-codesign; signal integrity; power integrity; EMC; power noise coupling; signal trace resonance I. INTRODUCTION Today’s CPU and chipset designers need to do more than simply make their systems operate under typical conditions in the laboratory. As the systems operate at 1GHz and beyond, a number of signal integrity (SI), power integrity (PI) and electromagnetic compatibility (EMC) issues become crucial to the overall system bandwidth. Conventional design flows separate the design of the power delivery network, the signal channel and EMC, therefore not accounting for the interactions among them. There has been some recent work considering both SI and PI design and analysis concurrently [1][2][3]. The design methodology proposed in this paper is a further unified solution to the co- design of signalling systems by proposing a new metric to unify PI and SI design, and by considering the attendant EMC issues. The concurrent approach considering SI-PI and EMC throughout the design as illustrated in Fig. 1 (a) is a fundamentally more cost-effective approach compared to a crisis-management approach. If the designer anticipates interactions between SI, PI and EMC at the beginning of the design process, and if noise suppression is considered for one stage or subsystem at a time, the noise mitigation techniques are simpler and more straightforward. If the designer proceeds with a disregard of various interactions until the design is close to being finished, mitigation techniques become considerably more costly, less effective and less available. Fig. 1 (b) summarizes this. In the co-design of SI-PI and EMC, several sources of coupled noise need to be considered in the signaling system that can degrade the quality of a transmitted signal. As the speed and width of interfaces increase, understanding these signal impediments and designing low cost solutions become ever more challenging. In a wide, single-ended signaling interface such as a DDR memory system, signals can contaminate one another through (1) crosstalk among adjacent signals, (2) power supply noise, and (3) radiation or electromagnetic interference (EMI). Item (1) is determined primarily by the cross-section of the signaling channel and is fairly well understood. Item (2) typically focuses on the noise experienced by the I/O buffer at the silicon die. Additional effects of power supply noise are described in Sections II and III. The source and mitigation of item (3) is discussed in Section IV. All three items are closely related since they are all due to the interaction of electromagnetic fields within the signaling system. (a) (b) Fig. 1 Concurrent design methodology 1-4244-1350-8/07/$25.00 ©2007 IEEE