Thermal Challenges to Gate Length Reduction of FET Ali M. Darwish 1 , H. Alfred Hung 2 1 American University in Cairo, AUC Ave., New Cairo, Egypt 11835 2 Army Research Laboratory, 2800 Powder Mill Rd., Adelphi, MD 20783 Abstract — The constant need for higher speed continues to lead to devices with shorter gate lengths, smaller gate widths, and gate finger spacing. The relationship of between various transistor parameters and the device lifetime is unclear due to the complexity of the problem, and the difficulty and expense of measuring reliability. This paper presents an analytical expression relating the reliability to a field effect transistor’s (FET) gate length, based on thermal considerations. Experimental observations support the model’s conclusions. Index Terms — FET; Channel Temperature; Thermal Resistance; Gate Length; Gate Width; Reliability. I. INTRODUCTION The reliability and performance of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) and Monolithic Microwave Integrated Circuit (MMIC) devices depend critically on the operating channel temperature. This quantity is usually used to predict devices lifetimes using the Arrhenius equation. The maximum allowed channel temperature drives the design of the cooling system, device package, and maximum DC/RF power limitations. Therefore, an accurate estimate of channel temperature is highly desirable. Several means [1]-[2] exist for measuring the thermal resistance and device channel temperature including Raman spectroscopy, forward diode voltage techniques, scanning thermal atomic force microscopy, liquid crystal techniques, and infrared microscopy. The channel temperature may be calculated by finite difference and finite element analysis. A number of accurate simulators have been developed based on finite volume, finite difference, and finite element techniques [3]-[5]. However, extracting channel temperature dependence on FET parameters is difficult using numerical methods because numerical analysis can study specific cases which may not be generalized. A highly accurate analytical model has been developed earlier [6]. The model takes into account the power dissipation, the self heating of each gate finger, the gate-gate heating, the substrates thermal conductivity and thickness, and the gate width. In this paper the full analytical model is used to calculate the dependence of reliability on the FET’s gate length. The deduced reliability expressions consider only the thermal effects. Additional factors resulting from design choices may further degrade (or improve) the reliability. For example, a short gate length influences the electric field intensity, required oxide thickness, and the fabrication quality which are directly connected with reliability. II. RELIABILITY-GATE LENGTH DEPENDENCE Consider a FET with a constant highly localized heat sources (Fig. 1) on a substrate of thickness t. The heat sources represent the gates of the device with length L g and width W g . The gate spacing is s, and the thermal conductivity is k. Fig. 1. FET dimensions. Gate dimensions are Lg x Wg, gate spacing s, substrate thickness is t. Based on [6], the thermal resistance per finger is ( ) ( ) ( ) ( ) ) ( ln 2 1 ) 3 . 2 ( ln 2 1 ])] [ ( [ ln 1 )] 1 ] 2 [ ( [ ln 1 s h k s t h k s L g f V k W s g f V k W g g g total π π π π θ - + - + = (1) where, 2009 International Conference on Microelectronics 978-1-4244-5816-5/09/$26.00 ©2009 IEEE 350