Characterizing a VLSI Standard Cell Library Mehmet A. Cirit Adaptec Inc. 691 South Milpitas Blvd. Milpitas, CA 95035 zyxwv ABSTRACT We describe a set of procedures for maintaining and characterizing an ASIC standard cell library. We have developed a modular zyxwvutsrq set of programs that generate timing parameters and associated documentation in a well integrated design environment. INTRODUCTION Accuracy and reliability of the electrical characteristics of the cells used in a standard cell design environment are crucial for the reliability and accuracy of any design using them. However, managing the large amount of information involved is not an easy task. Especially, zyxwvu as the feature sizes of VLSI chips shrink more and more fre- quently, maintenance and update of the electrical charac- teristics of the library elements may adversely affect the process of scaling existing designs to submicron techno- logies. While the functional and behavioral aspects of the circuit may not change as a result of the scaling or mov- ing to a new foundry, timing and performance are affected significantly. As a result, timing simulation and critical path analysis become important issues in porting existing designs to new technologies and foundries. Typically about fifty circuit level simulations are required to properly characterize a cell. These involve various combinations of temperatures, process comers, inputs signals and output loads. The likelihood that some errors will be introduced in the process is almost certain even for the most simple cases. In addition, the process has to be repeated for each layout release. Automating this laborious and lengthy process is important, as documen- tation of a cell and providing the information which should go into the data sheet is the last thing usually a cell designer thinks of, while it is the most important piece of information from the point of view of a system designer. Therefore making sure that the information flow between the back and front ends of the design cycle is reliable and accurate is essential. In this paper, we shall describe a system for characteriza- tion and documentation of a standard cell library. Input to the system is ideally a layout description in zyxwvutsr GDSII for- mat; its outputs are direct interfaces to the logic simulator and a data sheet for documentation purposes which is further processed by zyxwvutsrqp troffll]. We have written the entire characterization system, called ch, using standard UNIX facilities like sh, awk, ed, sed, cpp etc.. The circuit extractor and the circuit simulator are the only com- ponents which we have not provided ourselves. Plotting and documentation are handled by trofand pic[2]. There are other automated characterization systems reported in the literature[3-4]. The advantage of our approach is the separation of the stimuli databases from the process of parameter extraction. The circuit genera- tion is handled using a macro processor. This gives a lot of flexibility to specify the waveforms and the test condi- tions. Another advantage is the flexibility of our approach. We have been able to characterize intemal cells, input-output buffers, various custom blocks like register arrays and special purpose rams. The amount of code is about lo00 lines of awk and sh, which is extremely modest in view of the functionality. DATA FLOW Inputs to the characterization program are the cell representations in GDSII stream format, which is used for circuit and parasitic extraction. Characterizer accepts manually generated circuit descriptions as well. However, we feel that the layout based approach is safer, and actu- ally there were several instances where design errors has been detected because of the modeling inaccuracies in manually created circuit descriptions. Data flow is shown in Figure 1. The second input to the characterization is a stimuli file, a sample of which is shown in Figure 2. This file is pro- cessed by cpp, the C-preprocessor, before it is handed over to SPICE. Each one of the sections between zy # ifdef and # endif forms part of a complete SPICE input file which is used to calculate a particular parameter. The arguments to # ifdef conveys to ch, the characterization program, the name of the parameter extraction routine, or a particular flavor of it, and the name of thc parameter to be calculated. For example, the statement "# ifdef setup-sud" instructs ch to use the parameter extractor zyxw setup and name the calculated parameter as sud. Parameter names are prepended with the name of the cell before they are passed to the simula- tors and documentation generators. 25.7.1 IEEE 1 9 9 1 CUSTOM INTEGRATED CIRCUITS CONFERENCE CH2994-2/91/0000/0137 $1.00 ' 1991 IEEE