IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 12, DECEMBER 2007 2715 40-Gb/s High-Gain Distributed Ampliﬁers With Cascaded Gain Stages in 0.18- m CMOS Jun-Chau Chien, Student Member, IEEE, and Liang-Hung Lu, Member, IEEE Abstract—A novel circuit topology for high-gain distributed am- pliﬁers is presented in this study. Based on the conventional dis- tributed architecture, the gain cells are realized by cascading cas- code stages for gain enhancement. In addition, the stagger-tuning technique is extensively utilized in the design of the cascode stages as well as the cascaded stages, leading to signiﬁcant improvement in terms of the operating bandwidth and the gain ﬂatness. With the proposed circuit architecture, two ampliﬁers are implemented in a standard 0.18- m CMOS technology. The ampliﬁer with a 3 3 conﬁguration exhibits a gain of 16.2 dB and a 3-dB bandwidth of 33.4 GHz, while the one in a form of 2 4 demonstrates a gain of 20 dB and a bandwidth of 39.4 GHz. Consuming a dc power of 260 mW from a 2.8-V supply voltage, both circuits provide clear eye-opening with a pseudorandom bit sequence (PRBS) at 40 Gb/s. Index Terms—Bandwidth enhancement, distributed ampliﬁers, gain–bandwidth product, gain ﬂatness, inductive peaking, stagger- tuning technique. I. INTRODUCTION D UE TO THE increasing demand in the capacity of data communications, implementation of systems operating at a data rate beyond 10 Gb/s has attracted great attention in the past decade. With the advances in semiconductor technologies, integrated circuits operating at 40 Gb/s have been realized in standard CMOS processes [1]–[5]. Among all kinds of high- speed circuits, the broadband ampliﬁer is a key building block at both the transmitting and the receiving ends. Recently, sev- eral CMOS broadband ampliﬁers with bandwidth-enhancement techniques have been reported [6]–[10]. In conventional circuit implementations, the gain-bandwidth product of broadband ampliﬁers is severely limited by the process technology. For high-speed operations, the ampliﬁer gain is often sacriﬁced for an adequate bandwidth. Therefore, most of the 40-Gb/s ampliﬁers suffer from a limited gain [9], [10]. In order to overcome the design limitations, a novel circuit architecture for broadband ampliﬁers is proposed in this study [11]. By replacing the gain cells in the conventional distributed ampliﬁers (DAs) with cascaded stages, the gain is effectively enhanced. In addition, due to the use of inductive peaking with the stagger-tuning technique, a remarkable 3-dB bandwidth can be achieved while maintaining excellent gain ﬂatness within the entire frequency band. Manuscript received April 11, 2007; revised August 27, 2007. This work was supported in part by the National Science Council under Grants 96-2220-E- 002-016 and 96-2220-E-002-018. The authors are with the Department of Electrical Engineering and Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 10617, Taiwan, R.O.C. (e-mail: lhlu@cc.ee.ntu.edu.tw). Digital Object Identiﬁer 10.1109/JSSC.2007.908688 Fig. 1. Simpliﬁed circuit schematic of a 1-D DA. This paper is organized as follows. Section II discusses the existing architectures for broadband ampliﬁers and introduces the proposed circuit conﬁguration. Detailed circuit design and experimental results of the 40-Gb/s high-gain DAs are presented in Sections III and IV, respectively. Finally, conclusions are pro- vided in Section V. II. AMPLIFIER ARCHITECTURE A. Conventional DA Distributed circuit techniques are widely used for the broad- band ampliﬁers in high-speed data links [10]–[16] as well as the low-noise ampliﬁers in ultra-wideband (UWB) systems [17]–[19]. Fig. 1 shows the simpliﬁed schematic of the conven- tional one-dimensional (1-D) DA. Note that each gain cell is represented by a common-source stage for simplicity. By prop- erly choosing the transistor sizes and the inductance values, the input and the output of the ampliﬁer can be treated as 50- artiﬁcial transmission lines, demonstrating extremely wideband frequency response with low input and output return losses. In order to maximize the gain of the ampliﬁer, the phase delays of the input and the output transmission lines are typically matched. Therefore, the currents generated by the individual gain cells can be added constructively at the output of the ampliﬁer. Assuming that the transmission lines are lossless, the low-frequency gain of the 1-D DA can be estimated by (1) where is the number of the distributed stages, represents the transconductance of each stage, and is the termination impedance for the output transmission line, which is typically 50 . Note that the coefﬁcient 1/2 in (1) indicates that half of the signal current propagates in an opposite direction towards the drain termination. The characteristic impedance and the phase velocity of the artiﬁcial transmission lines can be expressed as (2) (3) 0018-9200/$25.00 © 2007 IEEE