Relaxing Synchronization in a Parallel SystemC Kernel Philippe Combes Eddy Caron Fr´ ed´ eric Desprez University of Lyon. LIP Laboratory. UMR CNRS - ENS Lyon - INRIA - UCB Lyon 5668. Bastien Chopard CUI, University of Geneva Julien Zory STMicroelectronics - now Honeywell Abstract SystemC has become a very popular standardized language for the modeling of System-On-Chip (SoC) devices. However, due to the ever increasing complexity of SoC designs, the ever longer simulation times affect SoC exploration potential and time-to-market. In order to reduce these times, we have developed a parallel Sys- temC kernel. Because theSystemC semantics require a high level of synchronization which can dramatically af- fect the performance, we investigate in this paper some ways to reduce the synchronization overheads. We val- idate then our approaches against an academic design model and a real, industrial application. 1. Introduction A typical System-on-Chip (SoC) development flow includes various activities that are most often han- dled by different groups with different profiles. Al- gorithm exploration, functional modeling, hardware- software integration, Register-Transfer Level (RTL) de- sign or verification are all part of that overall process. The SystemC [9] language was developed by the Open SystemC Initiative (OSCI) to enable system level de- sign and ease model exchange. It is promoted by sev- eral major EDA vendors and microelectronics compa- nies and it is today a very popular modeling solution in large scale programs. Engineers use a C++ based mod- eling platform to represent the functionality, commu- nications, software, and hardware components at mul- tiple levels of abstraction with a single common lan- guage. Note that in the rest of this paper, the term SystemC will refer to the system level modeling capa- bilities of SystemC 2.0.1. The ability to develop more and more complex sys- tems with completely virtual platforms and reasonably fast simulations is a key enabler for tomorrow’s success- ful SoC developments. More specifically, the conver- gence of multimedia technologies (MPEG4, MP4, etc.) with wireless connectivity (UMTS, WiMax, etc.) into new generation home and handheld consumer devices typically turns into very complex systems. Time-to- market is particularly critical for device manufacturers to build a true competitive advantage. One promising approach to reduce simulation times is parallel simulation. SystemC is most often used to describe the behavior of a complete system where several hardware and/or software components concur- rently perform some tasks. There are several possible approaches to exploit this inherent concurrency in par- allel simulation. Those extend from the basic use of OS threading on SMP’s [11], to complex distributed platforms [3, 7] which aim at providing IP (Intellectual Property) products for testing rather than increasing the simulation speed. However, to achieve fast simula- tion on cheap clusters of workstations, the best tracks come from the PDES field (Parallel Discrete Event Simulations), which has been widely studied in the 90’s [4, 5, 8]. Some simulators with specific custom languages have arisen from these concepts [10, 12, 14], but none were applied so far to a SystemC kernel 1 . We have developed a parallel version of the OSCI kernel based on the conservative approach to PDES, that proved to be efficient in some specific cases, but often suffers from high synchronization overheads [1, 2]. This paper explores some ways to reduce them. Sec- tion 2 first briefly describes SystemC and the algorithm of the public domain OSCI reference simulator. Then, using the same formalism, a model is given of our par- allel simulator prototype as it was published in [1]. Section 3 targets the reduction of the synchronization costs, focusing on data exchanges and synchronization of simulation time. The impact of our approaches are finally experimented and validated against a straight- forward pipeline application in Section 4 and a real- world industrial application in Section 5. 1 SimCluster, which is commercial software, is said to support SystemC: http://www.avery-design.com/web/avery_hdlcon02.pdf 2008 International Symposium on Parallel and Distributed Processing with Applications 978-0-7695-3471-8/08 $25.00 © 2008 IEEE DOI 10.1109/ISPA.2008.124 180 2008 International Symposium on Parallel and Distributed Processing with Applications 978-0-7695-3471-8/08 $25.00 © 2008 IEEE DOI 10.1109/ISPA.2008.124 180 2008 International Symposium on Parallel and Distributed Processing with Applications 978-0-7695-3471-8/08 $25.00 © 2008 IEEE DOI 10.1109/ISPA.2008.124 180 2008 International Symposium on Parallel and Distributed Processing with Applications 978-0-7695-3471-8/08 $25.00 © 2008 IEEE DOI 10.1109/ISPA.2008.124 180 Authorized licensed use limited to: TEL AVIV UNIVERSITY. Downloaded on November 23, 2009 at 08:59 from IEEE Xplore. Restrictions apply.