Fundamental Data Retention Limits in SRAM Standby – Experimental Results Animesh Kumar, Huifang Qin, Prakash Ishwar † , Jan Rabaey, and Kannan Ramchandran EECS, University of California, Berkeley, CA – 94720 † ECE, Boston University, Boston, MA – 02215 E-mail: {animesh,huifangq,jan,kannanr}@eecs.berkeley.edu, pi@bu.edu Abstract SRAM leakage power dominates the total power of low duty-cycle applications, e.g., sensor nodes. Accordingly, leakage power reduction during data-retention in SRAM standby is often addressed by reducing the supply voltage. Each SRAM cell has a minimum supply voltage parame- ter called the data-retention voltage (DRV), above which the stored bit can be retained reliably. The DRV exhibits significant intra-chip variation in the deep sub-micron era. As supply voltage is lowered, leakage power reduces, but a larger fraction of SRAM cells is prone to retention fail- ures. Use of appropriate error-correction to mitigate cell- reliability is proposed. Using this approach, the standby supply voltage is selected to minimize leakage power per useful bit. The fundamental limits on the leakage power per useful bit, while taking the DRV distribution into ac- count, are established. Minimization of power per bit re- sults in a supply-voltage at which a small fraction of cells fail to retain the data. For experimental DRV-distributions, a [31, 26, 3] Hamming code based implementation achieves a significant portion of the leakage power reduction com- pared to the fundamental limit. These analytical results are verified by twenty-four experimental chips manufactured in an industrial 90nm CMOS process. 1 Introduction Due to process variations and increasing memory size, SRAM or cache leakage power increases with scaling. This leakage power dominates the total power of low duty-cycle applications, e.g., sensor-nodes. For applications which are mainly in inactive or standby mode, dynamic voltage scal- ing (DVS) method is an effective way to reduce the leak- age power when the device (memory) is idle [1]. However, there is a limit to which SRAM cell’s voltage can be reduced while retaining data. Previous work has shown that, for any SRAM cell there is a critical supply voltage above which a data-bit is retained reliably. This voltage is called as the data-retention voltage (or DRV ) [2]. Due to process varia- tions, the DRV of different cells on a chip exhibits a wide range of values. Traditional worst-case solution suggests to fix the SRAM supply voltage at the largest intra-chip DRV value (say DRV max ) with supply-noise margin for success- ful retention [2]. Figure 1. Measured DRV distribution from an experimental 4 Kb SRAM chip manufac- tured in an industrial 90nm CMOS technol- ogy is illustrated. A typical intra-chip measured DRV distribution, from a previous test chip implemented in a 90nm, is illustrated in Figure 1 from a 90nm industrial CMOS technology. The largest observed DRV for the chip is DRV max = 190mV . The DRV max with supply-noise margin is the supply voltage for the worst-case strategy (say v max ). For power reduction below the worst-case strategy, a supply voltage lower than v max , with appropriate error-control coding to overcome en- suing errors, was proposed [3]. Under this approach, with the supply-voltage flexible and the DRV distribution as in Figure 1, it was shown that the leakage power per useful bit can be (fundamentally) reduced by approximately 40% (with respect to power consumption at supply voltage v max ), 9th International Symposium on Quality Electronic Design 0-7695-3117-2/08 $25.00 © 2008 IEEE DOI 10.1109/ISQED.2008.156 92 9th International Symposium on Quality Electronic Design 0-7695-3117-2/08 $25.00 © 2008 IEEE DOI 10.1109/ISQED.2008.156 92