One Error Control Scheme for ATM Header Peter Farkaš * , Martin Rakús * and Tomáš Páleník * * Slovak University of Technology/Department of Telecommunications, Bratislava, Slovakia, p.farkas@ieee.org Abstract— Wireless Asynchronous Transfer Mode (WATM) have been proposed by ETSI and ATM Forum for some communications applications. The ATM employs header error control (HEC) to protect the ATM cell header from bit error and/or avoid the miss forwarding of ATM cell. Standard HEC is based on CRC polynomial. Its decoding allows single error correction and it is usually based on ex- ploitation of look-up tables or other relatively complex pro- cedure caused by necessity to determine the position of the single error in a ATM cell header. This paper describes one additional FEC method for ATM cell header. The new ap- proach has slightly better error control capability and si- multaneously its decoding method is very simple and avoids the usage of look up tables. The FEC scheme is using the same redundancy as the standard method – 1 byte, but it allows correcting not only all single-bit errors in a header, but also some double-bit errors, triple-bit errors and quad- ruple-bit errors. I. INTRODUCTION Wireless asynchronous transfer mode (WATM) sys- tems have been proposed by ETSI and ATM Forum for some broadband communication applications [1]. The standard ATM employs header error control (HEC) to protect the ATM cell header from error and/or avoid the miss forwarding of ATM cell. Standard HEC is based on CRC-8 polynomial 1 ) ( 2 8     x x x x g . Its decoding allows single error correction and it is usually based on exploitation of look-up tables or on the other relatively complex procedure, which is avoiding the look up tables, which is proposed in [2]. This not very favorable fact is invoked by necessity to determine the position of the sin- gle bit error in ATM cell header. In [2] the following note well describes this situation: “Although the cyclic redun- dancy code (CRC) calculation is a well documented proc- ess, the determination of the position of the corrupted bit in a cell header is a laborious task and affects the circuit complexity and its maximum operational speed.” (It is well known that the common CRC decoding namely so- called syndrome decoding consist of two steps. At first the reminder of the division of the received word expressed as a polynomial by g(x) is calculated, and at second the error polynomial is determined by using a look up table, which stores all possible syndromes and corresponding error polynomials.) In [2] it is further argued: “The use of look up table cannot be considered as the optimal solution, since a part of the available silicon area is wasted for stor- ing this table. In some applications, the use of look up table is impractical, due to constraints imposed by the technology used and by the cost of additional circuitry.” This paper describes one other FEC method for ATM cell header. The new approach has slightly better error control capability and simultaneously its decoding method avoids the usage of look up tables. In practical applications of error control codes (ECC) very often the parameters as codeword length n, number of information symbols k have to be adapted to predefined values given by protocol. For example the protocol has a fixed number of symbols for payload and for redundancy. The proposed method is using the same redundancy as the standard ATM HEC scheme, namely 1 byte, but it allows correcting not only all single-bit errors in a header, but also many double-bit errors, triple-bit errors and quadru- ple-bit errors. Up to now the problem was solved as it is described in [2-9]. In the standard solution [2] ATM cell header (5 Bytes) is protected by one of the Bytes (the so called HEC-Byte), which allows correcting all single-bit errors in a 5-Byte header. The predefined space in this applica- tion is as follows. For information there are 4 Bytes = 32 bits and the space for redundancy is 1 Byte = 8 bits. The standard error control scheme used for protection of an ATM header can correct all single bit errors or detect some multiple-bit errors, but it cannot correct multiple-bit errors. In [3] two alternative codes were proposed for HEC, The first code with parameters [56,32,9] has much better error control capabilities than the standard one but its basic parameters are not compatible with the ATM header specification. Instead of 1 Byte redundancy it is using 3 Bytes. The other approach, described in [3], is using look up tables in order to compress the header in- formation and in the average it could be characterized by the following parameters [39,21,7]. However it still needs for its implementation look up tables in encoder as well as in decoder. Other known solutions are described in [4-8] which however also need much more redundancy than the standard approach. Most of these schemes use more than one error control code in concatenated arrangement or separate code for header and separate one for payload. For example in [4] the following codes were considered for AWGN channel: [461,406,11] BCH code over the entire header and payload, [61,22,15] BCH code over the header and a [411,384,7] BCH code over the payload and [61,22,15] BCH code over the header and a [420,384,9] BCH code over the payload and [61,22,15] BCH code over the header and a [429,384,11] BCH code over the payload. Finally the following code was selected as the best suiting the goals of tactical ATM: for HEC [82,40,13] and for ATM payload [421,376,11] code. Probably the best performance yet was achieved using Rate Compatible Punctured Turbo Codes [8], but at the cost of necessity to use computationally demanding iterative decoding proce- dures. On the other hand in [9] standard code parameters are used for HEC with special code construction, exploiting incomplete symbols. Its construction was proposed based on the codes constructed in [10], which followed from observation made in [11]. In case that this scheme is ap- plied to ATM cell header and an appropriate encoding and IEEE Region 8 SIBIRCON-2010, Irkutsk Listvyanka, Russia, July 11 -- 15, 2010 55 978-1-4244-7626-8/10/$26.00 ©2010 IEEE