A 60ns 500×12 0.35μm CMOS Low-Power Scanning Read-Out IC for Cryogenic Infra-Red Sensors F. Serra-Graells * , B. Misischi * , E. Casanueva † , C. Méndez † and L. Terés * * Institut de Microelectrònica de Barcelona (IMB), Centro Nacional de Microelectrónica - CSIC, Spain † Indra Sistemas S.A., Spain Abstract— This paper proposes a low-cost scanning read-out IC archi- tecture for large arrays of infra-red photon sensors operating at cryogenic temperatures. The low-power and compact 50μm×100μm active pixel sensor area is achieved by the use of novel CMOS basic building blocks for single-capacitor integration and correlated double sampling, embedded pixel-test, pixel charge-multiplexing, video multiplexing and offset calibration. As a result, a low-cost 500×12 and 60ns/pixel system- on-chip realization, capable of capturing high-resolution and real-time infra-red images like 640×500@100fps or 2560×500@25fps, is presented for a standard 0.35μm CMOS technology. I. I NTRODUCTION The increasing market demand on imaging applications in fields like medical, astronomy and strategic equipments requires read-out ICs (ROICs) capable of capturing high-resolution (i.e. >256×256 pixels 2 ) and real-time (i.e. >25fps) infra-red (IR) images. In general, IR sensing is primary supported in these systems by either photon or thermal devices [1]. The advantages of the former are higher sensitiv- ities and faster responses, while the latter exhibit room temperature operation and CMOS compatibility. In general, these IR devices are arranged in a fixed focal-plane array and attached one-by-one through bumping pads to the active pixel sensor (APS) cells of the CMOS ROIC. Unfortunately, the resulting large Si area of such ROICs tends to increase the prototyping cost, decrease the production yield and exhibit large power requirements for the final IR imaging system. This paper proposes an alternative strategy based on combining a scanning system architecture with novel low-power and compact circuit techniques, resulting in CMOS implementations with lower cost and power figures. In this sense, next section presents the overall system architecture, while Section III is devoted to explain in detail the new circuit techniques proposed for implementing each basic building block. Then, a complete ROIC for cryogenic photon sensors is presented in Section IV to demonstrate the feasibility of the design strategy proposed in this paper. Finally, conclusions are summarized in Section V. II. SYSTEM ARCHITECTURE The proposed system architecture is based on a linear imager, which builds the full frame by rotative scanning, as depicted in Figure 1(right). The imager itself includes an array of IR sensors vertically attached to the ROIC through a grid of detector-to-APS bumps, as shown in Figure 1(left). In our case, the IR plane is made of quantum-well infra-red photon sensors (QWIP) operating at cryogenic (77K) temperatures [2], which generate a positive detector- to-APS current proportional to the IR power according to their optical responsivity. The output video signal is generated by iterative scanning along the full column of pixels. Although the system structure behaves as a single-column effective imager, in practice several physical columns of pixels are implemented to allow color images and time-delay integration (TDI). The main advantage of the scanning architecture of Figure 1 is the small area requirements for the final ROIC compared to the Fig. 1. Proposed architecture for the imaging system. equivalent fixed focal-plane solution, resulting in a low-cost and improved yield CMOS integration. Furthermore, an optimum trade- off can be achieved between frame size and refresh time for each particular imaging application. On the other hand, the APS cell must be compact and fast enough to meet the system specifications concerning spatial resolution and multiplexing times. Also, all the ROIC basic building blocks must be designed under low-power restrictions to be compatible with their cryogenic operation. III. LOW-POWER AND COMPACT CIRCUITS The following subsections introduce novel low-power and com- pact CMOS basic building blocks to implement all the processing functionalities requested in Figure 1. A. Single-Capacitor CTIA and CDS Pre-amplification of the sensor current signal (Iqwip) is usually achieved through a capacitive transimpedance amplifier (CTIA). Due to the extremely small values of the integration capacitance (Cint ), an extra correlated double sampling (CDS) stage is usually needed to eliminate KTCint noise [3]. A classical circuit implementation of both functions is shown in Figure 2(upper), where CCDS , V refi and V pixel stand for the CDS capacitance, the input bias voltage of the IR sensor and the output signal voltage, respectively. However, such implementation require two capacitors per pixel, resulting in a large cell size. In order to save APS area, a new single- capacitor implementation is proposed in Figure 2(lower). Instead of resetting Cint before each integration period (Tint ), the basic idea is to pre-charge it by differential sampling (i.e. reset) to the output offset and low-frequency noise of the CTIA, so causing proper cancellation during the integration phase. Hence, the same capacitor C int/CDS is devoted here to perform both the integration and CDS 1742 0-7803-8834-8/05/$20.00 ©2005 IEEE.