Improving the energy efficiency of reversible logic circuits by the combined use of adiabatic styles Mehrdad Khatir à , Alireza Ejlali, Amir Moradi Department of Computer engineering, Sharif University of Technology, Azadi Ave., Tehran, Iran article info Article history: Received 15 October 2008 Received in revised form 16 January 2010 Accepted 24 September 2010 Keywords: Adiabatic logic Reversible circuits Landauer’s principle Breaking reversibility abstract One of the most prominent issues in fully adiabatic circuits is the breaking reversibility problem; i.e., non- adiabatic energy dissipation in the last stage adiabatic gates whose outputs are connected to external circuits. In this paper, we show that the breaking reversibility problem can result in significant energy dissipation. Subsequently, we propose an efficient technique to address the breaking reversibility problem, which is applicable to the usual fully adiabatic logic such as 2LAL, SCRL, and RERL. Detailed SPICE simulations are used to evaluate the proposed technique. The experimental results show that the proposed technique can considerably reduce (e.g., about 74% for RERL, 35% for 2LAL, and 17% for SCRL) the energy dissipation arising from the breaking reversibility problem. & 2010 Elsevier B.V. All rights reserved. 1. Introduction Nowadays, many digital circuits are targeted at portable and battery-operated systems; consequently, the energy minimization has become a primary concern when designing such systems. Several techniques are utilized to curb the energy dissipation by means of reducing dynamic and leakage power consumption. In systems which have significant switching activity, dynamic power is a dominant factor in energy dissipation. Therefore, amongst numerous dynamic power reduction techniques, charge recovery [13,14] seems to be attractive because it exploits a different type of charging which yields a high energy efficiency gain [5,6]. The charge recovery concept has several circuit implementations such as [1,3,8,15,20,22]. Among these imple- mentations, reversible styles [1,3,22] are more preferable due to Landauer’s principle [4,16]. Moreover, these styles have inherently a redundant gate structure which can be exploited to resist single event upset (SEU) in NoC networks [7]. However, when a reversible style is utilized, a problem arises related to the reversibility nature of such circuits. The problem namely ‘‘breaking reversibility’’ is that irreversibility, which always appears in the last stage of reversible circuits, causes a considerable non-adiabatic energy dissipation. Some researchers have ignored the effect of breaking reversibility problem since they have only considered adiabatic circuits with a large number of stages, e.g., an inverter chain with 512 stages [17,18]. Since breaking reversibility problem only arises for the last stage of adiabatic circuits, when using adiabatic circuits with a large number of stages, the energy overhead of the breaking reversibility problem can be neglected compared with the total energy consumption of all stages. In [22], tapered buffers have been used to reduce the energy dissipation in the output node of the last stage. However, the energy dissipation of the last buffer of a tapered buffer chain is still large if the non-adiabatic loss, which is due to a supply-voltage drop, exists in the last buffer stage [19]. In [19], some attempts have been made to recover the energy of the last stage gates in a common reversible style, RERL [3]. However, there are still some non- adiabatic dissipations that can be reduced. To the best of our knowledge, this paper is the first comprehensive attempt to reduce the energy consumption caused by ‘‘breaking reversibility’’ with combined use of reversible fully adiabatic circuits and irreversible semi-adiabatic ones. In our proposed techniques, semi-adiabatic irreversible styles are modified in such a way that they follow the design constraints of reversible fully adiabatic structures, e.g., timing constraints and switching thresholds. The simulation results show that using our proposed techniques, the total energy consumption of the whole circuit decreases in average about 42% for a 10-stage combinational circuit in different logic styles. The rest of the paper is organized as follows. In Section 2, the concept of charge recovery is explained. In Section 3, the available reversible circuits are described and analyzed. Section 4 presents the problem description. Our proposed semi-adiabatic terminals are introduced in Section 5. The experimental results are presented in Section 6. The conclusions are finally given in Section 7. 2. Charge recovery concept The principle of the adiabatic charging scheme can be best explained by contrasting it with conventional method during the Contents lists available at ScienceDirect journal homepage: www.elsevier.com/locate/vlsi INTEGRATION, the VLSI journal 0167-9260/$ - see front matter & 2010 Elsevier B.V. All rights reserved. doi:10.1016/j.vlsi.2010.09.004 à Corresponding author. E-mail addresses: khatir@ce.sharif.edu (M. Khatir), ejlali@sharif.edu (A. Ejlali), a_moradi@ce.sharif.edu (A. Moradi). INTEGRATION, the VLSI journal 44 (2011) 12–21