EMBEDDED APPLICATION PROTOTYPING ON A COMMUNICATION- RESTRICTED RECONFIGURABLE PLATFORM Arif Sasongko Amer Baghdadi Frederic Rousseau Ahmed Amine Jerraya SLS Group, TIMA Laboratory, 46, Av. Felix Viallet, 30831, Grenoble, France {Arif.Sasongko, Amer.Baghdadi, Frederic.Rousseau, Ahmed.Jerraya}@imag.fr Abstract As the complexity of SoC is increasing, prototyping becomes more and more suitable than simulation to validate the design. Reconfigurable platform is the solution to attain this prototyping in realistic cost and time. Unfortunately, most of the reconfigurable platforms have fixed communication network. This property becomes a restriction to implement the nowadays applications which have very complex and sophisticated communication network. In this paper we present a novel approach for embedded application prototyping using reconfigurable platform under communication restriction. The effectiveness of our approach is illustrated through an application example using an ARM Integrator platform. 1. Introduction Hardware/Software validation is becoming one of the most critical issues in current SoC development flows. As SoCs increase in complexity, validation becomes more and more difficult, time consuming, and error prone. A modern SoC contains a great amount of embedded software and a large number of heterogeneous components: processors, DSPs, memories, sophisticated communication networks, and a set of hardware blocks (IPs). Moreover, it usually interfaces other complex components: banks of SDRAM, serial links, I/Os, and other complex subsystems. Using simulation in order to validate such a system involves generation of complex heterogeneous test benches and simplified models of the SoC environment. In addition, it lacks accuracy and it is time-consuming (few seconds of real time can take several hours or days of simulation). With emerging complex applications, simulation may even become impossible. Thus building a hardware prototype becomes inescapable in order to ensure fast execution speed. The current practice when building a hardware prototype for a complex SoC is to design an application-specific prototype. This approach is expensive in terms of man- power and time-to-prototype. Therefore, we need a highly reconfigurable prototyping platform to ensure reusability of the platform. Such a prototyping platform, in the case of hardware/software SoCs, must enable simultaneously hardware and software development. This means that it must enable an early software debug (the critical path in system design). To that end, the prototyping platform must enable an accurate micro-architecture model as close as possible to the designer view. This means that it must comprise the real processor cores to execute the software. Thus, the probability to obtain first-time silicon success is highly increased thanks to the accuracy of the prototype. On the other hand, for architecture exploration issues, and in order to cope with the severe time-to-market constraints, the prototyping flow must be automatic in order to ensure fast prototyping. The problem encountered in most existing platforms is limitation in the communication part. Most platforms have a fixed communication network between their modules. Designer should find a way to cope with this restriction. We present in this paper a novel approach for complex SoC prototyping in order to solve the problem described previously. The prototype, in our case, is aimed for emulation. Emulation means execution of the application on an intermediate technology (reconfigurable platform) which is close to the final implementation (silicon). The rest of this paper is organized as follows. Section 2 introduces the hardware/software architecture model and the platform model for prototyping. Section 3 classifies existing platforms into several categories and presents ARM Integrator platform. Section 4 presents the SoC prototyping flow and our prototyping techniques. Section 5 presents ideal prototyping process and prototyping process under communication constraints. Section 6 illustrates the efficiency of the proposed approach through an application example. Finally, section 7 gives conclusions and presents our perspectives for this work. 2. SoC Models for Prototyping 2.1 Hardware/Software architecture model A generic RTL architecture model for SoC is given in Figure 1.a [1]. This architecture model divides the application into three software parts and four hardware parts. The software parts, which run on processors, are application software, operating system (OS), and hardware abstraction layer (HAL). The hardware parts are processors, communication wrappers, communication networks, and IP cores. Draft version