JoVDTT (2016) 1-12 © STM Journals 2016. All Rights Reserved Page 1 Journal of VLSI Design Tools & Technology ISSN: 2249-474X (online), ISSN: 2321-6492(print) Volume 6, Issue 2 www.stmjournals.com A New TGC-Differential Input Stage to Modify Dynamic Comparator Anurag Sharma 1 , Gurinderpal Singh 2 * Chandigarh University, Gharuan, Punjab, India Abstract As the technology rapidly scaling down, the escalating demand for higher accuracy is putting a heavy pressure to find ways to get rid of one of the major issues among present day dynamic comparators i.e. random offset voltage generation. A number of offset calibration techniques have been presented to resolve this issue. It has become an important concern to analyze these techniques for scaled down technology nodes to cop up with modern day dynamic latched comparators. In this paper, the input stage of comparator is modified for offset minimization and a better high frequency response. The proposed topology is verified by simulating in ‘Synopsys Custom-designer’ environment using 32/28 nm-integrated technology node. The simulation results shows improvement in random offset generation and delay for the common mode range of 0.6 V and low voltage supply of 0.8 V with the capability of detecting input voltage difference up to 0.5 mV over some of the recent works. The structure operates at a higher speed with a delay reduction from 113 ps to 46 ps at approximately the same energy dissipation of 50 μW/GHz at a higher frequency of 4 GHz. The results obtained from 100 samples of transient ‘Monte-Carlo simulations’ shows minimization in offset generation with 1-sigma input referenced offset of 0.38 mV at the latch stage without any digital calibration schemes saving large area. Keywords: TGC, mixed-signal, frequency response, offset calibration, mismatches *Author for Correspondence E-mail: live.anurag61@gmail.com INTRODUCTION The comparator is a crucial circuit that fills the analog-digital boundary in modern day mixed- signal integrated circuit design. Being the true mixed signal circuit it plays a crucial role in high-speed analog to digital converters. For the overall successful implementation of a data converter system, the most crucial part is the design and implementation of the comparator with ensuing performance. The comparator can broadly be classified into two categories namely: static and dynamic. The static is one which includes threshold detection based on input reference signal without any clocking mechanism. These are found to be simple and quiet easy to design but found mere application in modern world’s high-speed ADC’s. The second one is dynamic comparator based on the clocking mechanism defining the speed of comparator and hence characterizes the performance of ADC. This comprises of a regenerative latch to provide positive feedback and hence, called dynamic latched. The conventional dynamic comparator is an analog to digital conversion device with two analog inputs and a single output. A lot of dynamic latch comparators have been presented in past with different topologies showing a drastic reduction in offset voltage than the pre-amplifier based comparators [1– 6]. In the last few years most of the researchers have been trying to minimize the random offset voltage to provide an ultra-high speed, low-voltage, low-power comparator fighting against various process challenges with scaling down [7–9]. At the moment flash ADC has been the architecture of prime importance having sampling frequency of 2 to 40 GS/s and a resolution of 4-6-bit, with applications where high-speed and low resolution are vital. On the other hand, there is conciliation on the performance and complexity while going for such ADC [3, 4]. Moreover, as the technology scales down the problem with these comparator topologies that trouble is the large chip area being occupied by the various digital