Stochastic simulation of material and process effects on the patterning of complex layouts D. Drygiannakis 1 , N. Tsikrikas 1 , G. P. Patsis 1 , G. Kokkoris, I. Raptis 1 , E. Gogolides 1 , 1 Institute of Microelectronics, NCSR Demokritos, Athens, 15310 Greece Phone: +30-210-6503116 Fax: +30-210-6511723 E-mail: gpatsis@imel.demokritos.gr ABSTRACT The whole process of stochastic lithography simulation combined with an electron-beam module, could be useful in the validation of design rules taking into account fine details such as line-edge roughness, and for simulating the layout before actual fabrication for design inconsistencies. Material and process parameters can no more be considered of second order importance in high-density designs. Line-width roughness quantification should accompany CD measurements since it could be a large fraction of the total CD budget. An example of the effects of exposure, material and processes on layouts are presented in this work using a combination of electron beam simulation for the exposure part, stochastic simulations for the modeling of resist film, the post-exposure bake, resist dissolution, and a simple analytic model for resist etching. Particular examples of line-width roughness and critical dimension non-uniformity due to, material, and process effects on the gate of a standard CMOS inverter layout are presented. Keywords: lithography, etching, process, simulation, LER, LWR, mask, layout, design, LER transfer with etching 1. INTRODUCTION The time gap between technology nodes has accelerated in recent years (e.g. between 130nm and 90nm there was less than a 2 year gap, and between 90nm and 65nm a 1.5 year gap exists [1]). As a result, the technical challenges have increased substantially. Future device generations will have to perform alterations in the layout based on process information to improve yield. Given the increasing cost of IC fabrication, patterning simulation of the layout prior to tapeout should be carried out in order to facilitate the IC designers with more accurate data. Those data could be used for further layout optimization. There are several simulators available for the simulation of either electron beam lithography or line edge roughness. However, to the authors’ knowledge, an integrated simulator capable to handle the high resolution patterning over complex layouts is not available. With these problems in mind, a home made stochastic lithography simulator [2], along with a 3D e-beam exposure-pattern-convolution module [3] are integrated in order to result in a complete lithography simulator to account for high resolution layouts. The choise of e-beam simulation is not limiting. The aerial image and energy deposition from any other advanced optical (193nm or EUV) simulator could be used, and would be more important for industrial applications. However, we decided to use our in-house e-beam simulator in order to demonstrate the proposed methodology, and have complete control in the transfer of information among the various modules. The application of stochastic modeling techniques is preferred in the sub-100nm length scales probed with this simulator because all microscopic phenomena can be considered, through appropriate assignment of occurrence probabilities. This way it is also easier to incorporate new phenomena in the framework. The whole process could be useful in the validation of design rules taking into account line-edge roughness (LER) and for simulating the layout before actual fabrication for design inconsistencies. Examples of the effects of exposure, material and processes on layouts will be presented in this work using the above simulation approach. Specifically, the whole simulation process will be applied on the mask levels of an inverter layout and the metrology of critical dimensions and line-width roughness on the p- and n-type transistors will be correlated with the exposure, resist material and processing parameters of the mask layers.