Advanced CMOS Transistors in the Nanotechnology Era for High-Performance, Low-Power Logic Applications (Invited Paper) Robert Chau*, Mark Doczy, Brian Doyle, Suman Datta, Gilbert Dewey, Jack Kavalieros, Ben Jin, Matthew Metz, Amlan Majumdar, and Marko Radosavljević Components Research, Logic Technology Development, Intel Corporation 5200 N.E. Elam Young Parkway, Mailstop: RA3-252, Hillsboro, OR 97124, USA *Email: robert.s.chau@intel.com Abstract Sustaining Moore’s Law requires continual transistor miniaturization. Through silicon innovations and breakthroughs, CMOS transistor scaling and Moore’s Law will continue at least through early next decade. By combining silicon innovations with other novel nanotechnologies on the same Si platform, it is expected that Moore’s Law will extend well into the next decade. This paper describes the most recent advances made in silicon CMOS transistor technology and discusses the challenges and opportunities presented by the recent emerging nanoelectronic devices such as carbon nanotube field-effect transistors (FET), Si-nanowire FETs and III-V FETs for high-performance, low-power logic applications. 1. Introduction Moore’s Law states that the number of transistors per integrated circuit doubles every 24 months, and it has been the guiding principle for the semiconductor industry for over 30 years. In order to sustain Moore’s Law, the physical gate length (L g ) of the transistor has been scaled by ~30% every generation, as shown in Fig. 1. The current 90 nm generation technology node produces CMOS devices with L g of ~50 nm. It is projected that the L g of the transistor will reach ~10 nm in 2011 [1]. Through silicon technology innovations and breakthroughs such as metal-gate/high-K stacks [2]-[4], uniaxially strained Si channels [5], [6], biaxially strained Si and SiGe channels [7], [8], and the non-planar fully-depleted Tri-gate CMOS transistor architecture [9], [10], CMOS transistor scaling and Moore’s Law will continue at least through early next decade. Recently, tremendous progress has been made in the research of novel nanoelectronic devices such as carbon nanotube FETs [11], [12], Si-nanowire FETs [13], [14], and III-V compound semiconductor FETs [15], [16]. These novel devices present both challenges and opportunities for future nanoelectronics applications [17]. By combining Si innovations with the novel nanotechnologies onto the same Si platform, it is expected that circuit functionality can be greatly enhanced and Moore’s Law will be extended well into the next decade. 2. Si Breakthrough: High-K/Metal-Gate Stacks for High-Performance Si CMOS For more than 15 years the physical thickness of SiO 2 has been aggressively scaled for high-performance, low-power CMOS applications [2]. Recently SiO 2 with physical thickness of 1.2 nm has been successfully implemented in the 90 nm logic technology node [18]. In addition, SiO 2 with physical thickness of 0.8 nm [see Fig. 2(a)] has been demonstrated in the laboratory [1], [24], and has been integrated into 15 nm L g Si research transistor, whose TEM cross-section is shown in Fig. 2(b) and drain current vs gate voltage (I d -V g ) characteristics shown in Fig. 3. Continual gate oxide scaling, however, will require high-K materials since gate oxide leakage is increasing with decreasing SiO 2 thickness and since SiO 2 is running out of atoms for further scaling. So far, the most common high-K dielectric materials investigated are Hf-based and Zr-based [2], [3]. Technology Node 0.5µm 0.35µm 0.25µm 0.18µm 0.13µm 90nm 65nm 45nm 30nm Transistor Physical Gate Length 130nm 70nm 50nm 30nm 20nm 15nm 1995 2005 1990 2000 2010 1995 2005 1990 2000 2010 0.01 0.1 1.0 Micrometer Nanotechnology 10 100 1000 Nanometer 10 100 1000 Nanometer Transistor Scaling Year Figure 1. Scaling of transistor size (physical gate length L g ) to sustain Moore’s Law.