Temperature-controlled coalescence during the growth of Ge crystals on deeply patterned Si substrates Roberto Bergamaschini a,n , Marco Salvalaglio a , Andrea Scaccabarozzi a , Fabio Isa b , Claudiu V. Falub b,1 , Giovanni Isella c , Hans von Känel b , Francesco Montalenti a , Leo Miglio a a L-NESS and Department of Materials Science, Università di Milano-Bicocca via R. Cozzi 55, I-20126 Milano, Italy b Laboratory for Solid State Physics, ETH Zürich Otto-Stern-Weg 1, CH-8093 Zürich, Switzerland c L-NESS and Department of Physics, Politecnico di Milano via F. Anzani 42, I-22100 Como, Italy article info Article history: Received 28 July 2015 Received in revised form 25 January 2016 Accepted 29 January 2016 Communicated by D.W. Shaw Available online 6 February 2016 Keywords: A1. Growth models A3. Chemical vapor deposition processes B2. Semiconducting germanium B2. Semiconducting silicon abstract A method for growing suspended Ge films on micron-sized Si pillars in Si(001) is discussed. In [C.V. Falub et al., Science 335 (2012) 1330] vertically aligned three-dimensional Ge crystals, separated by a few tens of nanometers, were obtained by depositing several micrometers of Ge using Low-Energy Plasma-Enhanced Chemical Vapor Deposition. Here a different regime of high growth temperature is exploited in order to induce the merging of the crystals into a connected structure eventually forming a continuous, two- dimensional film. The mechanisms leading to such a behavior are discussed with the aid of an effective model of crystal growth. Both the effects of deposition and curvature-driven surface diffusion are con- sidered to reproduce the main features of coalescence. The key enabling role of high temperature is identified with the activation of the diffusion process on a time scale competitive with the deposition rate. We demonstrate the versatility of the deposition process, which allows to switch between the formation of individual crystals and a continuous suspended film simply by tuning the growth temperature. & 2016 Elsevier B.V. All rights reserved. 1. Introduction The evolution of microelectronics toward new device concepts increasingly requires materials with different chemical, crystal- lographic and thermal properties to be combined on a silicon chip [1]. This demand is potentially met by two main competing technologies, wafer bonding [2] and epitaxial growth [3]. Germa- nium is a well-established choice for several optoelectronic applications, such as near-infrared detectors [4] and it has been recently reconsidered, both by academic and industrial research, as a high-mobility hole-channel material for the mainstream sili- con MOSFET technology [5]. Despite decades of investigations, Ge on Si epitaxy remains challenging, mainly because the 4.2% lattice misfit causes a Ge film to relax through misfit dislocations above a small critical thickness. Several approaches have been proposed to reduce the density of detrimental threading dislocations which accompany misfit dislocations, such as graded Si x Ge 1  x buffer layers [6], aspect-ratio-trapping [7,8], post-growth thermal treat- ments [9], and composite AlAs/GaAs buffer layers [10]. As an alternative approach, in Ref. [11] we have shown that the deposition of tens of microns of Ge on top of dense arrays of high- aspect ratio Si pillars can lead to self-aligned vertical structures, separated by few dozens of nanometers, allowing for an almost full space-tessellation. This was achieved by performing the growth in a kinetic regime determined by low temperature (400– 500 °C) and high deposition rates (  4 nm/s), obtained by Low- Energy Plasma-Enhanced Chemical Vapor Deposition (LEPECVD). Independently of the growth method, frustrated diffusion and mutual flux shielding between the neighboring crystals were found to be the key factors yielding this peculiar three- dimensional growth mode [12,13]. Interestingly, it was observed that the top morphology of such structures grown by LEPECVD can be finely tuned, from an almost (001) flat at low growth tem- peratures to a pyramidal shape bounded by {113} facets at high temperatures [14]. In this latter case, no dislocations were found at the crystal top [15,16], making them a good candidate for high- performance device fabrication [17,18]. Recent results [19,20] even showed the possibility to completely avoid misfit dislocations by adopting graded layers on the Si pillars. While several applications may comply with, or even profit of, pixelation, for most of the technological purposes, e.g. for CMOS hetero-integration, a continuous film is highly demanded. Different methods have been explored in the literature in order to fabricate Contents lists available at ScienceDirect journal homepage: www.elsevier.com/locate/jcrysgro Journal of Crystal Growth http://dx.doi.org/10.1016/j.jcrysgro.2016.01.035 0022-0248/& 2016 Elsevier B.V. All rights reserved. n Corresponding author. E-mail address: roberto.bergamaschini@mater.unimib.it (R. Bergamaschini). 1 Present address: Evatec AG, Hauptstrasse 1a, CH-9477 Trübbach, Switzerland. Journal of Crystal Growth 440 (2016) 86–95