International Journal of Engineering Research ISSN:2319-6890)(online),2347-5013(print) Volume No.5, Issue No.7, pp : 560-563 1 July 2016 IJER@2016 doi : 10.17950/ijer/v5s7/702 Page 560 Performance Analysis of Quasi-Cyclic Low Density Parity Check Codes 1 Nalini Prasad Tirumani , 2 Patchigolla Subbarao Department of E.C.E, S.R.K.R Engineering College, Bhimavaram, Andhra Pradesh, India. 1 naliniprasadt@gmail.com, 2 patsrao@gmail.com Abstract: Low-Density Parity-Check codes are the class of linear block codes, which perform the near Shannon limit performance on data transmission. Here, Quasi Cyclic codes are circulant permutation matrices, for the efficient encoding purpose. In this paper, QC-LDPC Codes have significant performance improvement due to the effective iterative Min- Sum decoding algorithm in terms of Bit Error Rate (BER) versus E b /N o with low and high code rates compared to other existing codes. Soft decision decoding and increased number of iterations of QC-LDPC codes has better performance. Index Terms: LDPC codes, Quasi-Cyclic codes, QC- LDPC codes, Min-Sum Decoding Algorithm. I. INTRODUCTION In order to have reliable communication, over noisy channels, error correcting codes are used. Error correcting codes [1] insert redundancy into the transmitted data stream and receiver possibly correct errors that occur during transmission. There are several types of codes exist. Every code has some special application. Researchers are searching for the best code for wireless communication application. In this paper propose a particular type of error correcting code called LDPC. LDPC Codes originally introduced by Gallager [2] in 1960’s. However , it was impossible to implement the code in hardware at that time. Three decades later LDPC Codes rediscovered by Mackay and Neal [3] due to its excellent properties of the code and its current feasibility. LDPC Codes have proven to have very good performance over noisy channels. The main reason is that the error performance is very close to Shannon limit [3], [4]. The main advantage of the LDPC codes is this its performance is very close to turbo codes, however, LDPC codes allow parallel decoding architectures, thus achieving higher throughput as compared to turbo codes. Error correcting capability of turbo codes can be suppressed by LDPC codes; at the same time, the hardware complexity of LDPC codes tends to be significantly smaller than that corresponding to turbo codes. LDPC Codes further classified into two types LDPC Block codes (LDPC- BCs) and LDPC Convolutional Codes(LDPC-CCs). LDPC codes [5] are explained by their parity check matrix and the way this is connected. LDPC codes are classified into two types, namely regular and irregular codes. In regular LDPC number of ones in row and column weights is equal. Whereas in irregular type number of ones in row and column weights are not same. The more important approach that proposed in this paper is to design circulant LDPC codes with permutation blocks [6]. Due to the block circulant structure of the parity check matrix encoding done very efficiently. These structures allow for small storage requirement, as well as for performing encoding and via fast and simple circuits. Such high-speed architectures are of crucial importance in communications. The code generated by an intersection of quasi-circulant (Quasi-Cyclic) [6], [7], [8] codes. A quasi-circulant code of is a code with a property that any cyclic shift of a codeward in some positions represents another code word. Additionally, the Min- Sum decoding algorithm [9], [10] employed for soft-decision decoding of these requires a number of binary logic operations at least one order of magnitude smaller than that corresponding to hard-decision decoding of turbo codes. The rest of the paper is as follows. Section II describes the overview of LDPC codes & Quasi-cyclic codes. The next section III proposed QC-LDPC coding and decoding techniques. In section IV various performance results and appropriate comparisons, while conclusion in section V. II. OVERVIEW OF LDPC CODES & QUASI-CYCLI CODES In this section a brief overview of LDPC blocks codes. These codes will be used as a reference for the purpose of proposed QC-LDPC codes. A. LDPC block codes Low-Density Parity Check Codes (LDPC) codes, are the class of linear block codes. The name Low Density comes from characteristics of their parity check matrix contains only a few number of 1’s in comparison to 0’s. Basically, LDPC codes represented by two ways, one is matrix representation and second possibility is graphical (Tanner Graph) representation. In matrix representation, there are two numbers describing the parity check matrix with dimension n x m. w r for the number of 1’s in each row and w c for the column. A matrix to be called low-density there is two conditions w r <<min (m, n) and w c <<min (m, n) must be satisfied [5]. Graphical representation of parity check codes by the tanner graph. Tanner graph not only representing the complete code but also help to describe the decoding algorithm. There are two types nodes in Tanner graph are called variable nodes (v-nodes) and check nodes (c- nodes).The bellow shows the matrix representation and corresponding graphical representation of the Low-Density Parity Check Code ) 1 ( 0 1 0 1 1 0 0 1 1 1 1 0 0 1 0 0 0 0 1 0 0 1 1 1 1 0 0 1 1 0 1 0              H