IU( LLAR PHYSIC: II liPl PROCEEDINGS SUPPLEMENTS ELSEVIER Nuclear Physics B (Proc. Suppl.) 78 (1999) 625-634 w-.vw.elsevie r. nl/locate/n pe Deep submicron CMOS technologies for the LHC experiments P. Jarron 1, G. Anelli 1, T. Calin 4, J. Cosculluela 4, M. Campbell 1, M. Delmastro 1'3, F. Faccio I , A. Giraldo 2 E. Heijne j , K. Kloukinas 1, M. Letheren ~, M. Nicolaidis 4, P. Moreira 1, A. Paccagnella 2, A. Marchioro 1 W. Snoeys 1, R. Velazco 4 CERN, 1211 Geneva 23, Switzerland 2 University of Padova University of Padova & INFN, via Marzolo 8, 35131 Padova, Italy 3 Supported by Associazione per 1o Sviluppo Scientifico e Tecnologico del Piemonte, Italy 4 TIMA/INPG Laboratory, 46 Avenue Felix Viallet, 38031 Grenoble, France The harsh radiation environment at the Large Hadron Collider (LHC) requires radiation hard ASICs. This paper presents how a high tolerance for total ionizing dose can be obtained in commercial deep submicron technologies by using enclosed NMOS devices and guard rings. The method is explained, demonstrated on transistor and circuit level, and design implications are discussed. A model for the effective W/L of an enclosed transistor is given, a radiation-tolerant standard cell library is presented, and single event effects are discussed.. 1 INTRODUCTION The front end electronics in the detectors planned at the new accelerator at CERN, the Large Hadron Collider (LHC), will be subject to very high radiation levels : up to - 30 Mrad equivalent for ionizing dose, and about 1015 neutrons/cm 2. For several years, the High Energy Physics (HEP) community has studied and evaluated radiation hard technologies suitable for developing mixed-signal ASICs for the readout of these LHC experiments[ 1,2,3]. In the mean time, the market of radiation tolerant circuits for defense has shrunk considerably, and the Space community has started to use more Commercial-Off-The-Shelf (COTS) components rather than the more expensive and less advanced Hi- Rel components used in the past. This evolution and the fast growth of the semiconductor business in other areas has caused several semiconductor companies to abandon the radiation hard electronics market, and now only a very few companies in the world offer radiation-hard technologies suitable for LHC front- end ASICs. Already in the early 80's irradiation measurements on MOS capacitors [4,5] showed a significant decrease of the radiation induced trapped charge in the oxide and interface states lbr oxides thinner than about 10 nm. Gate oxides in present day submicron CMOS technologies are in this range. The market trend mentioned above, and these early results on thin oxide MOS capacitors were the motivation for us to investigate an alternative approach based on radiation-tolerant design techniques in deep submicron CMOS technology. By employing "enclosed" geometry and guard rings in the layout of NMOS devices we eliminate the radiation- induced leakage paths along the edges of devices and between devices. Recent results [6,7,8,9,10,11,12] have confirmed the tremendous potential of this approach. In section 2 the approach is explained, transistor measurements are presented, and design implications discussed. In section 3 the modelling of a transistor laid out in enclosed geometry is investigated in more detail. In section 4 results on circuit demonstrators are presented. Section 5 discusses the newly designed digital library, and section 6 deals with single event effects. Thereafter conclusions are drawn and perspectives for the future are given. DESIGN FOR RADIATION TOLERANCE IN DEEP SUBMICRON TECHNOLOGY 2.1 Radiation induced transistor threshold voltage shift For CMOS technologies with minimum feature size above - lp.m, the threshold voltage shift which results from hole trapping in MOS gate oxides decreases as the square of the oxide thickness [13]. The 1970's CMOS technologies exhibited more than 1Volt of shift after l0 krad, whereas 0.5p.m technology exhibits a shift of less than 150 mV after 300 krad. As already pointed out, early measurements [4,5] on MOS capacitors indicated a sharp decrease (much sharper than the forementioned square law would indicate) in radiation induced trapped charge and interface states for oxides less than 10 nm thick. There it was suggested that tunnelling could be the mechanism behind this observation, because it would 0920-5632/99/$ - see front matter © 1999 ElsevierScience B.V. All rights reserved. PII S0920-5632(99)00615-5