Low Temperature Germanium Growth on Silicon Oxide Using Boron Seed Layer and In Situ Dopant Activation Munehiro Tada, a,b,z Jin-Hong Park, a Duygu Kuzum, a, * Gaurav Thareja, a Jinendra Raja Jain, a Yoshio Nishi, a, ** and Krishna C. Saraswat a a Department of Electrical Engineering, Stanford University, Center for Integrated Systems, Stanford, California 94305, USA b NEC Corporation, Device Platforms Research Laboratories, Kanagawa 229-1198, Japan Low temperature  350°C growth of germanium Ge on silicon dioxide  SiO 2  is demonstrated using a diborane pretreatment technique. Using SiH 4 and B 2 H 6 precursors, Si 1-x B x layers are deposited on SiO 2 to seed the chemical vapor deposition growth of Ge films. In the SiH 4 :B 2 H 6 system, the binary deposition mechanism of the Si 1-x B x film is explained by the “enhancement” model. In situ doping of Ge films is also investigated. In situ boron activation is achieved during the crystallization of the Ge films at 310°C. Device applicability of the doped Ge film growth on oxide is demonstrated in a low temperature  350°C Si p-channel metal-oxide-semiconductor field-effect transistor, in which the Ge layer is used as a gate electrode. The low temperature Ge growth technique can be used for low thermal budget processes, e.g., monolithic three-dimensional integrated circuits. © 2010 The Electrochemical Society. DOI: 10.1149/1.3295703 All rights reserved. Manuscript submitted August 13, 2009; revised manuscript received December 22, 2009. Published February 4, 2010. Complementary metal oxide semiconductor scaling has led to the high performance and low power operation of ultralarge-scale inte- gration devices. 1-3 However, scaling transistors to the nanometer regime is plagued with many challenges, including gate leakage, mobility degradation, reliability issues, and increasing vulnerability to random process variations. Recently, 45 nm node devices com- prising high-k/metal gate and strained-channel technologies have been commercially produced. 4 However, due to growing standby power consumption as a consequence of device shrinking, further scaling is experiencing serious roadblocks. Soon, scaling will cer- tainly face physical limits, requiring a paradigm shift to monolithic three-dimensional 3D integrated circuits ICs. 5,6 Monolithic 3D-IC technology has several benefits compared to other approaches, e.g., wafer-to-wafer, chip-to-wafer, and chip-to- chip bonding. Monolithic 3D-IC provides increased logic density without a serious 3D wafer-to-wafer alignment problem as well as complicated, deep via fabrication. In addition, the monolithic ap- proach is free from the yield degradation problem, which plagues the device wafer stacking method. While promising for future tech- nologies, monolithic 3D-IC fabrication is still challenging. Devices must be fabricated above copper interconnects that incorporate frag- ile, porous, low dielectric constant materials. 7,8 To realize the mono- lithic 3D-IC, high quality Si and Ge channels and low temperature process technologies for gate oxide, gate electrode, and source/drain S/D are required. To grow Ge films on SiO 2 without damaging the material layers underneath, a low temperature low pressure chemical vapor deposition LPCVD technique is desired. Conventionally, an LPCVD Si layer deposited at 500°C is used as a seed for Ge growth on SiO 2 . 9 However, this approach is not applicable to the monolithic 3D-ICs. Low temperature processes  350°C are thus required to preserve the underlying interconnects and devices. In this paper, we focus on low temperature Ge growth on silicon dioxide and low temperature Ge process technologies as vehicles for realizing monolithic 3D-ICs. We have developed a low temperature LPCVD Ge growth technique using a seed approach, which is po- tentially useful for low resistance gate electrodes as well as high mobility channels. 10 Specifically for the gate electrode application, the Ge layer formed by conformal LPCVD can be used for 3D channel structures, such as double-gate and Fin-type transistors. The applicability of our doped LPCVD Ge film process has been dem- onstrated in Si p-channel metal-oxide-semiconductor field-effect transistors PMOSFETs using a fully low temperature plasma gate oxide 11 and Schottky S/D technologies for monolithic 3D-ICs. Experimental The starting substrates were Si wafers n-type, 5–10  cm with 200 nm silicon dioxide  SiO 2  grown by wet thermal oxidation. The wafers were cleaned in 4:1 H 2 SO 4 :H 2 O 2 at 90°C for 10 min and 5:1:1 H 2 O:HCl:H 2 O 2 at 70°C for 10 min, followed by deion- ized water rinse and N 2 drying. The Ge film was deposited in an LPCVD epi chamber Applied Materials Epi Centura using a pure GeH 4 precursor. Hydrogen 6 slpm was used as a carrier gas. Be- fore the Ge deposition, a boron-based pretreatment was used to pre- pare the wafer surface at 350°C for 1 min. This pretreatment was done using a diborane  B 2 H 6  precursor diluted to 1% by hydrogen in some cases and B 2 H 6 /SiH 4 mixture gas for other samples. The substrate temperature was then changed to 310°C to grow a germa- nium film on SiO 2 using GeH 4 precursor. In situ doped p- and n-type Ge films were grown by using B 2 H 6 and PH 3 precursors, respec- tively, during the Ge film growth. Dopant activations was done at temperatures below 350°C. Si PMOSFETs using the in situ boron-doped Ge gate electrode process were integrated with a radical oxidizing gate dielectric and Schottky Pt silicide S/D at temperatures below 350°C. The starting substrates were Si wafers n-type, 5–10  cm, which were cleaned in 4:1 H 2 SO 4 :H 2 O 2 at 90°C for 10 min and 5:1:1 H 2 O:HCl:H 2 O 2 at 70°C for 10 min, followed by deionized water rinse and N 2 drying. A plasma oxidation technique 12 was used to form the low temperature gate oxide. Specifically an 8.3 nm gate oxide was formed using a slot plane antenna SPA plasma system with 3.4 kW and 2.45 GHz microwave under 50 mTorr, O 2 /Ar chemistry at 350°C Tokyo Electron Trias. 13 After gate oxide for- mation, the in situ boron-doped Ge films were deposited on the oxide using various pretreatment conditions. A thin low temperature oxide LTO film was subsequently deposited as a cover layer to enhance photoresist adhesion. The Ge film and most of the plasma SiO 2 dielectric were dry-etched to form the gate electrode. After removing the LTO layer and the remaining SiO 2 on the top of the S/D regions by using 2% HF, 5 nm Pt was deposited using a metal evaporator. The prepared samples were annealed at 350°C for 1 h to form a silicide in the source and drain regions. The film thickness of the deposited Ge on SiO 2 was determined by secondary electron microscopy SEM. Surface roughness of the Ge films was measured by atomic force microscopy AFM. X-ray photoelectron spectroscopy XPS was used to analyze the surface composition of SiO 2 after the pretreatment and to detect dopants in the in situ doped Ge film deposition. Ge film crystallization was examined by X-ray diffraction XRDCu K,  = 1.5408 Å. * Electrochemical Society Student Member. ** Electrochemical Society Active Member. z E-mail: m-tada@bl.jp.nec.com Journal of The Electrochemical Society, 157 3 H371-H376 2010 0013-4651/2010/1573/H371/6/$28.00 © The Electrochemical Society H371 Downloaded 17 May 2010 to 171.64.101.175. Redistribution subject to ECS license or copyright; see http://www.ecsdl.org/terms_use.jsp