COM2 SiGe Modular BiCMOS Technology for Digital, Mixed-Signal, and RF Applications M. Carroll, T. Ivanov, S. Kuehne, J. Chu, C. King*, M. Frei *, M. Mastrapasqua”, R. Johnson*, K. Ng*, S. Moinian*, S. Martin*, C. Huang, T. Hsu, D. Nguyen, R. Singh, L. Fritzinger, T. Esry, W. Moller, B. Kane, G. Abeln, D. Hwang, D. Orphee, S. Lytle, M. Roby, D. Vitkavage, D. Chesire, R. Ashton, D. Shuttleworth, M. Thoma, S. Choi, S. Lewellen, P. Mason, T. Lai, H. Hsieh, D. Dennis, E. Harris, S. Thomas, R. Gregor, P. Sana, and W. Wu Bell Laboratories,Lucent Technologies - Orlando, FL and *Murray Hill, NJ Abstract The COM2 SiGe modular BiCMOS technology has been developed to allow efficient design and manufacturing of digital, mixed-signal, and RF integrated circuits, as well as enabling system-on-chip (SOC) integration. The technology is based on the 0.16pm COM2 digital CMOS process which features ISV NMOS and PMOS transistors with 2.4nm gate oxide, 0.135pm gate length, and up to 7 metal levels. Technology enhancement modules including dense SRAM, SiGe NPN bipolar transistor, and a variety of passive components have been developed to allow the COM2 technology to be cost-effectively optimized for a wide range of applications. Introduction A BiCMOS process with modular integration of embedded memory, a high-performance SiGe NPN transistor, and passive components into an advanced CMOS process is a promising solution for many communication SOC designs [ 1,2]. However, few technologies with a high-speed SiGe NPN transistor and with CMOS beyond 0.18l.t.m have been reported. In this paper, the COM2 SiGe modular BiCMOS technology is presented which includes 0.135pm gate-length CMOS, a SiGe NPN transistor with fT of 58GHz, as well as critical passive components. Technology Description A. COM2 Digital CMOS Core Process The O.lbpm 1.5V/3.3V COM2 CMOS process uses p- epi/p+ substrate, shallow trench isolation, dual gate oxides, and dual-doped tungsten polycide gate. The process also offers up to 7 aluminum metal levels with tungsten plug vias and FSG inter-level dielectric. The high-performance 1.5V NMOS and PMOS transistors feature 0.135pm minimum gate length and 2.4nm gate oxide, resulting in a ring oscillator delay of 22ps/stage. Fig. 1 shows typical IO-Vcs characteristics, and Fig. 2 shows V,.ii, vs. gate length. Fig. 3 shows the typical 2.4nm gate oxide reliability data from time dependent dielectric breakdown (TDDB) measurements. The absence of extrinsic oxide failures indicates a high quality oxide. The average failure rate for the oxide on a chip operating for 25 years under worst case bias conditions is predicted to be less than 0.25FIT. Low-power NMOUPMOS transistors are also available in the COM2 CMOS process with low off current of lOpA/pm. In addition, 3.3V NMOWMOS transistors with aggressive 5.Onm gate oxide and high drive currents of 700/400 PA/pm are also available. B. Derlse SRAM The standard 6T SRAM cell for the COM2 technology has an area of 5.7pm2. A dense SRAM cell with an area of 3.31.tm2 is also available by tightening selected design rules and with the addition of one mask level for a self-aligned and borderless contact. Non-volatile memory cells are also used to implement redundancy in dense memory arrays using one additional mask level [3]. C. SiGe NPN Bipolar Transistor The SiGe bipolar transistor module adds a low-cost, high- performance, super-self-aligned (double-poly) graded SiGe base NPN transistor to the COM2 process. The NPN transistor module requires just four additional mask levels, using high-energy phosphorus implantation for the sub- collector and selective epitaxy for the SiGe base [2,4]. The emitter is formed using in-situ arsenic doped poly. The SiGe bipolar module also does not alter the COM2 digital CMOS device parameters. Standard shallow trench isolation is used to isolate bipolar transistors. Relaxed spacing between the NPN sub-collector and adjacent CMOS p-tub is used to reduce the lateral Ccs. The SIMS profile of a completed NPN transistor is shown in Fig. 4. The Ic. Ia, and common-emitter current gain, B, vs. Vas are shown in Fig. 5 for a typical NPN transistor. The base and collector currents both show ideal 60mV/decade current slope down to the picoampere range, resulting in relatirely constant current gain over a wide range of collector current. The collector characteristics are shown in Fig. 6, demonstrating BV~E~ of 3.6V and high Early voltage, VA, of 60V. The NPN transistor was specifically optimized for BVcEo of 3.6V to accommodate a wide range of designs with a single NPN transistor. 7.1 .I O-7803-6438-4/00/$ IO.00 02000 IEEE IEDM 00- 145 For individual use by an IEEE Electron Devices Society member purchasing this product.