Design of Prototype Scientific CMOS Image Sensors Paul Vu, Boyd Fowler, Chiao Liu, Janusz Balicki, Steve Mims, Hung Do, and Dan Laxson Fairchild Imaging 1801 McCarthy Blvd., Milpitas, CA 95035, USA ABSTRACT We present the design and test results of a prototype 4T CMOS image sensor fabricated in 0.18-μm technology featuring 20 different 6.5 μm pixel pitch designs. We review the measured data which clearly show the impact of the pixel topologies on sensor performance parameters such as conversion gain, read noise, dark current, full well capacity, non-linearity, PRNU, DSNU, image lag, QE and MTF. Read noise of less than 1.5e- rms and peak QE greater than 70%, with microlens, are reported. Keywords: Scientific CMOS image sensors, high-speed imager, low readout noise, 4T pixel design 1. INTRODUCTION Major technical advances have been reported recently in CMOS image sensor technology including the development of advanced digital/analog circuit designs and improvements in device fabrication technologies. Imager performance parameters such as sensitivity, noise, speed and power have shown substantial improvements [1][2][3]. However, many commercially available products do not meet the demanding requirements of advanced scientific applications in terms of noise, speed, and power. As part of our internal product development process for a new scientific-grade CMOS image sensor which is intended to address the performance limitations outlined above, Fairchild Imaging is performing an extensive, multi-phase investigation on the impact of circuit architecture and pixel topology on key sensor performance parameters such as read noise, dark current, image lag, full well capacity, quantum efficiency (QE), and modulation transfer function (MTF). Our goals are to debug and optimize critical elements of the design on prototype devices, demonstrate the desired performance, and validate the product sensor specifications. We focus on a 0.18-μm 4T CMOS image sensor (CIS) process technology which supports dual voltage operation: 1.8V for the high-speed digital logic circuitry and 3.3V for the analog components. The basic 4T pixel architecture consists of a pinned photodiode, a reset transistor, a transfer gate to move charge from the photodiode to the floating diffusion sense node, a source follower transistor, and a row select transistor. In the first phase of the project, our goals were to evaluate various pixel design parameters, determine how they influence the imaging properties of the sensor, and develop low noise high speed column parallel readout circuitry with integrated correlated double sampling (CDS). The prototype sensor included 36 different pixel designs with variations intended to optimize full well capacity, read noise, dark current, lag and MTF. In the second phase, the key design goals included further performance optimization of the pixel and the low noise column parallel amplifier design. Then in the third phase of the project, the best performing pixel designs will be implemented in an area array format and integrated with low noise 12-bit column parallel analog-to-digital converters. The completed sensor will provide complete digital input control and digital pixel data. Our primary design goals are to demonstrate a sensor design which will satisfy the requirements for sensitivity, noise and speed in advanced scientific applications. To date, we have completed the first two phases of the project, and the results of the first phase were reported last year [4]. In the first prototype sensor, we measured read noise as low as 1.9 e - rms at 30 Mpixels/sec and a dark current density less than 11 pA/cm 2 at 30ºC. The measured full well capacity was 1.4 ke - in high gain mode and 30 ke - in low PRE-PRINT: SPIE Astronomical Telescopes and Instrumentation, 23-28 June 2008, Marseille, France Paper #7021-2 to be published in Proceedings of SPIE Vol. 7021