IEEE ELECTRON DEVICE LETTERS, VOL. 35, NO. 12, DECEMBER 2014 1167 Defect-Centric Distribution of Channel Hot Carrier Degradation in Nano-MOSFETs Luis Miguel Procel, Felice Crupi, Senior Member, IEEE , Jacopo Franco, Member, IEEE, Lionel Trojman, Member, IEEE, and Ben Kaczer Abstract— The defect-centric distribution is used, for the first time, to study the channel hot carrier (CHC) degradation. This distribution has been recently proposed for bias temperature instability (BTI) shift and we show that it also successfully describes the CHC behavior. This distribution has the advantage of being described by two physics-based parameters, the average threshold voltage shift produced by a single charge η and the number of stress-induced charged traps N t . We study the behavior of η and N t on nFETs with different geometries for different CHC stress times. As in the case of BTI, we observe that: 1) during the CHC stress, η is constant and N t increases at the same rate of V th and 2) η scales as 1/Area. We show that the density of charged traps induced by CHC stress strongly increases with reducing channel length, in contrast to BTI, where the density of charged traps is independent of the device geometry. The defect analysis enabled by the defect- centric statistics can be used to deepen our understanding of CHC degradation in nanoscale MOSFETs, where the defects are reduced to a numerable level. Index Terms— nFET, channel hot-carrier, defect-centric distribution. I. I NTRODUCTION C HANNEL hot-carrier (CHC) is one of the most criti- cal degradation mechanisms affecting the performance of modern CMOS devices [1]–[8]. In spite of the huge amount of papers devoted to CHC degradation, there is still a limited number of studies on the statistical distribution of CHC-induced degradation in nanoscale devices [4]–[8]. Recently, the so-called Defect-Centric distribution has been proposed for predicting the bias temperature instability (BTI) induced degradation [9]–[11]. It has been reported that the Defect-Centric distribution can correctly predict the extreme Manuscript received August 1, 2014; revised September 22, 2014 and September 29, 2014; accepted September 30, 2014. Date of publication October 20, 2014; date of current version November 20, 2014. This work was supported by the European Union under the 7th Framework Programme through the Collaborative Project MORDRED under Contract 261868. The work of L. M. Procel and L. Trojman was supported by the Universidad San Francisco de Quito’s Chancellor Grants Programme in 2013. The review of this letter was arranged by Editor L. Selmi. L. M. Procel is with the Università della Calabria, Rende 87036, Italy, and also with the Universidad San Francisco de Quito, Quito EC170157, Ecuador (e-mail: lprocel@usfq.edu.ec). F. Crupi is with the Dipartimento di Ingegneria Informatica, Modellistica, Elettronica e Sistemistica, University Nano Electronics Team, Università della Calabria, Rende 87036, Italy. J. Franco and B. Kaczer are with imec, Leuven 3001, Belgium. L. Trojman is with the Universidad San Francisco de Quito, Quito EC170157, Ecuador. Digital Object Identifier 10.1109/LED.2014.2361342 tails of the BTI shift distribution up to 4σ [12]. The ability of Defect-Centric distribution for predicting the BTI behavior has been demonstrated in five generations of Intel technologies (from 90 nm to 22 nm) featuring different materials and architectures [13]. The Defect-Centric distribution is based on two assump- tions: the threshold voltage shift produced by a single charged trap is exponentially distributed, while the total number of charged traps is Poisson-distributed [9], [10]. The model takes into account both, the traps located in the oxide, as well as those located at the interface [11]; the effect of the latter is the dominant CHC degradation mechanism in ultra-short channel lengths and ultra-thin gate oxides [1]. The basic equations describing the Defect-Centric distribution are: H η, N t (V th ) =  ∞ n=0 e -N t N n t n!  1 - n n! Ŵ(n,V th /η)  (1) 〈V th 〉= N t η (2) σ 2 = 2 N t η 2 (3) where H η, Nt is the cumulative Defect-Centric distribution, η is the mean value of V th produced by a single charge (exponential distribution), N t is the dimensionless mean value of the total number of charged traps per device (Poisson distribution), 〈V th 〉 is the expected value of H η, Nt and Γ is the Gamma function [9]. It is relevant to mention that the parameters extracted from the 1 st and 2 nd statistical moment equations (Eqs. 2 and 3) have a physical meaning, thus enabling us to perform a defect analysis of the degraded device. This type of analysis is extremely useful to physically understand the CHC degradation of nanoscale MOSFETs in terms of individual defects. The purpose of this letter is to investigate if the Defect-Centric framework can also predict successfully the behavior of CHC degradation in nanoscale MOSFETs. II. EXPERIMENTAL SETUP CHC measurements have been performed on bulk planar nFETs with gate dielectrics consisting of 1.8 nm of SiON. In order to study the geometry dependence of CHC distribu- tion, we selected nFETs with an effective channel length L eff varying between 40 nm and 120 nm and a channel width W varying between 70 nm and 200 nm. The standard measure-stress-measure (MSM) technique was used for stressing the devices. We used the most degrading 0741-3106 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.