182 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 18, NO. 1, FEBRUARY 2005 Self-Aligning Planarization and Passivation for Integration Applications in III–V Semiconductor Devices Hilmi Volkan Demir, Jun-Fei Zheng, Vijit A. Sabnis, Onur Fidaner, Student Member, IEEE, Jesper Hanberg, James S. Harris, Jr., Fellow, IEEE, and David A. B. Miller, Fellow, IEEE Abstract—This paper reports an easy planarization and passi- vation approach for the integration of III–V semiconductor de- vices. Vertically etched III–V semiconductor devices typically re- quire sidewall passivation to suppress leakage currents and pla- narization of the passivation material for metal interconnection and device integration. It is, however, challenging to planarize all devices at once. This technique offers wafer-scale passivation and planarization that is automatically leveled to the device top in the 1–3- m vicinity surrounding each device. In this method, a dielec- tric hard mask is used to define the device area. An undercut struc- ture is intentionally created below the hard mask, which is retained during the subsequent polymer spinning and anisotropic polymer etch back. The spin-on polymer that fills in the undercut seals the sidewalls for all the devices across the wafer. After the polymer etch back, the dielectric mask is removed leaving the polymer sur- rounding each device level with its device top to atomic scale flat- ness. This integration method is robust and is insensitive to spin-on polymer thickness, polymer etch nonuniformity, and device height difference. It prevents the polymer under the hard mask from etch- induced damage and creates a polymer-free device surface for met- allization upon removal of the dielectric mask. We applied this inte- gration technique in fabricating an InP-based photonic switch that consists of a mesa photodiode and a quantum-well waveguide mod- ulator using benzocyclobutene (BCB) polymer. We demonstrated functional integrated photonic switches with high process yield of 90%, high breakdown voltage of 25 V, and low ohmic contact resistance of 10 . To the best of our knowledge, such an integra- tion of a surface-normal photodiode and a lumped electroabsorp- tion modulator with the use of BCB is the first to be implemented on a single substrate. Index Terms—Integrated optoelectronics, passivation, semicon- ductor device manufacturing, wafer-scale integration. I. INTRODUCTION I N today’s III–V semiconductor technology, 50%–80% of the total cost typically comes from device packaging. Such high packaging cost means we should minimize chip packaging in Manuscript received January 1, 2003; revised November 2, 2004. This work was supported in part by Intel Corporation and by PTAP (funded by the National Science Foundation and the Defense Advanced Research Projects Agency). H. V. Demir is with the Edward L. Ginzton Laboratory and Solid State and Pho- tonics Laboratory, Stanford University, Stanford, CA 94305 USA and also with Nanotechnology Research Center, Bilkent University, Bilkent Ankara TR-06800 Turkey (e-mail:volkan@bilkent.edu.tr; volkan@stanfordalumni.org). J. F. Zheng is with Intel Strategic Technology, Intel Corporation, Santa Clara, CA 95052 USA. V. A. Sabnis is with Translucent, Inc., Palo Alto, CA 94303 USA. O. Fidaner, J. S. Harris, Jr., and D. A. B. Miller are with the Edward L. Ginzton Laboratory and Solid State and Photonics Laboratory, Stanford University, Stan- ford, CA 94305 USA. J.HanbergiswithGIGAApS,IntelCorporation,DK-2740Skovlunde,Denmark. Digital Object Identifier 10.1109/TSM.2004.841834 any subsystem incorporating III–V semiconductor devices. This might be achieved, for example, by integrating multiple III–V devices on a single chip. This is, however, not a straightforward task. One of the difficulties stems from a III–V device passiva- tion requirement that creates planarization and interconnection problems. In conventional etch-back planarization methods [1], it is challenging to achieve planarization across the entire wafer so that the integrated device sidewalls are all sealed and passi- vated, especially where the top layers are only submicrometer thick. In this paper, we introduce a novel wafer-scale integra- tion method using a polymer that passivates the sidewalls all the way to the top of the layered heterostructure across the wafer. This method provides self-aligning planarization and passiva- tion across the wafer. In our integration method, the sidewalls of III–V devices are completely passivated with a polymer that self-planarizes flush with the device top to an atomic flatness in the vicinity of the de- vices across the entire wafer. The process is illustrated in Fig. 1 and consists of the following steps: 1) defining a dielectric hard mask on the (epitaxial) wafer, which is retained for the sub- sequent steps; 2) defining the semiconductor device area with the use of the hard mask by vertically etching the unmasked parts of the wafer; 3) selectively etching the sidewalls of the semiconductor structure in the lateral direction to create an un- dercut beneath the hard mask; 4) sealing and passivating the sidewalls of all device layers under the hard mask with a spin-on polymer; 5) etching back the cured polymer past the top level of the hard mask with an anisotropic dry etch; and finally 6) re- moving the hard mask to create a passivation structure, with the polymer around the device perimeter completely level with the device top. Depending on where the polymer etch-back process is stopped with respect to the hard mask and the semiconductor device, various final polymer profiles might be obtained for dif- ferent purposes. The undercut renders this integration technique robust and in- sensitive to spin-on polymer thickness, polymer etch nonunifor- mity, and device height difference. The undercut structure also protects the polymer under the hard mask from etch-induced damage. Furthermore, when the hard mask is removed, a clean, polymer-free device surface is left for metallization. Also, if desired, stopping the polymer etch back within the hard mask thickness, self-aligned via-like structures can be obtained for easy metallization [2]. In a similar approach, even without the use of an undercut, a relatively thick hard mask allows a more re- laxed margin for the etch depth of the polymer and a larger thick- 0894-6507/$20.00 © 2005 IEEE