Analytical threshold voltage model for short-channel asymmetrical dual-gate material double-gate MOSFETs A. Tsormpatzoglou a,⇑ , I. Pappas a , D.H. Tassis a , C.A. Dimitriadis a , G. Ghibaudo b a Department of Physics, Aristotle University of Thessaloniki, 54124 Thessaloniki, Greece b IMEP, MINATEC, Grenoble, France article info Article history: Available online 1 May 2011 Keywords: Dual material Double gate Short channel Potential distribution Threshold voltage Analytical model abstract An analytical threshold voltage model in undoped short-channel DG MOSFETs with asymmetrical dual gate material is presented. The threshold voltage model is derived based on an analytical solution for the potential distribution along the channel in the subthreshold region. For verification of the model, the potential distribution along the channel length and the threshold voltage are compared with simula- tion results for a wide range of the device dimensions. Ó 2011 Elsevier B.V. All rights reserved. 1. Introduction The double-gate (DG) MOSFET in undoped ultra-thin layers is considered the most attractive device for ultimate scaling of CMOS technology due to its excellent short-channel effects (SCEs) immu- nity [1–5]. To enhance the immunity to SCEs, a new dual-material DG MOSFET, consisting of two metal gates (p + polysilicon and n + polysilicon) with different work functions has been proposed [6], which provides simultaneous suppress of SCEs and increase in transconductance. In this configuration, a threshold voltage model has been developed, using a graphical method based on numerical simulation [7]. Recently, a physics-based semi-analytical threshold voltage has been derived for dual-material DG MOSFETs, verified for devices with gate length down to 60 nm [8]. In the present work, we develop a physics-based fully analytical threshold volt- age model in dual-material DG MOSFETs, which is verified by com- paring the model with simulation results in devices with channel length down to 30 nm. 2. Potential distribution model The cross-section of the DG MOSFET is shown in Fig. 1. The channel is divided into two regions: Region 1 of length L 1 repre- senting an asymmetrical DG MOSFET with different top and bottom gate metals of work functions U m1 and U m2 referenced to the intrinsic silicon and region 2 of length L 2 representing a sym- metric DG MOSFET with work function U m2 for both top and bot- tom metal gates. For the high gate work function it is assumed U m1 = 5.25 eV to stand for the p + polysilicon and for the low gate work function U m2 = 4.17 eV to stand for the n + polysilicon. The po- tential distributions u 1 (x, y) and u 2 (x, y) in regions 1 and 2, respec- tively, satisfy the boundary conditions: u 1 ðy ¼ 0Þ¼ V bi , u 1 ðy ¼ L 1 Þ¼ V o , u 2 ðy ¼ L 1 Þ¼ V o and u 2 ðy ¼ LÞ¼ V bi þ V d , where V d is the drain voltage and V bi is the built-in potential at the source/drain junctions. When the ratio of channel length/silicon thickness is >2, the solutions of Poisson’s equation in regions L 1 and L 2 are [9]: u 1 ¼ 1 e 2L 1 k  1 ðV o  A 1 Þ e L 1 þy k  e L 1 y k   þðV bi  A 1 Þ e 2L 1 y k  e y k   h þ A 1 ðe 2L 1 k  1Þ i ð1Þ u 2 ¼ 1 e 2ðLL 1 Þ k  1 ðV bi þ V d  A 2 Þ e L2L 1 þy k  e Ly k   h þ V o  A 2 Þ e 2LL 1 y k  e yL 1 k   þ A 2 ðe 2LL 1 k  1Þ  i ð2Þ where V g is the gate voltage, A 1 ¼ V g þ C 1 and A 2 ¼ V g  U ms2 with C 1 ¼ 2e 2 Si t ox N a qt ox t Si þ e ox ðU ms1 þ U ms2 Þ ½ þ e 2 ox N a qt Si xðx  t Si Þ 2e ox e Si ð2e Si t ox þ e ox t Si Þ  e ox e Si 2e ox ðt Si U ms1  U ms1 x þ U ms2 xÞþ N a qt ox ðt 2 Si þ 2t Si x  2x 2 Þ   2e ox e Si ð2e Si t ox þ e ox t Si Þ : ð3Þ 0167-9317/$ - see front matter Ó 2011 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2011.04.065 ⇑ Corresponding author. E-mail address: atsormpa@auth.gr (A. Tsormpatzoglou). Microelectronic Engineering 90 (2012) 9–11 Contents lists available at ScienceDirect Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee