IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 9, SEPTEMBER 2006 2091 Analytical Modeling of Output Conductance in Long-Channel Halo-Doped MOSFETs Sivakumar Mudanai, Member, IEEE, Wei-Kai Shih, Rafael Rios, Member, IEEE, Xuemei (Jane) Xi, Member, IEEE, Jung-Hoon Rhew, Kelin Kuhn, and Paul Packan Abstract—In this paper, a detailed physical analysis and an analytical derivation of the degradation of the output resistance (R out ) observed in relatively long-channel laterally nonuniformly doped devices with halo implants are presented. Two-dimensional device simulations were performed, and the simulations show that the channel can be split into two uniformly doped transistors in series for the purpose of analysis. The lower doped bulk transistor is on the source side, while the higher doped halo transistor is toward the drain end. Based on this two-transistor analysis, a simple R out degradation model is derived for implementation in a MOSFET compact model. Index Terms—Compact model, halo, MOSFET, output- resistance degradation. I. INTRODUCTION T RADITIONALLY, CMOS devices have been optimized for digital performance, although recently, the same tech- nology is being used in the development of RF and analog components [1]. One of the key variables used in this optimiza- tion process is the halo or pocket implant [2]–[5]. There are several models that describe the result of using halo implants on threshold voltage [6]–[8]. While this implant successfully reduces the drain-induced barrier lowering (DIBL) for short channel lengths, it causes a severe degradation of the output resistance for longer channel lengths [9]. In [10], a simplified analytical expression was derived, but a physical explanation was never offered. The impact of the pocket implants on the output resistance (R out ) degradation is also discussed in [11], but the explanation presented only goes so far as to say that the presence of barriers on both source and drain causes lower early voltages for long-channel transistors. In fact, the barrier reduction on the drain side due to the drain bias is modeled as long-channel DIBL in compact models [7], [10], but the output- resistance degradation caused by this model is insufficient to explain the R out degradation observed in the on region [10]. Hence, an additional mechanism is required to model the R out degradation observed in the on region. Understanding and com- Manuscript received February 1, 2006; revised May 5, 2006. The review of this paper was arranged by Editor S. Saha. S. Mudanai and J. Rhew are with the Compact Device-Modeling Group, Intel Corporation, Hillsboro, OR 97124 USA (e-mail: Sivakumar.p.mudanai@ intel.com). W.-K. Shih is with TCAD, Intel Corporation, Hillsboro, OR 97124 USA. R. Rios and X. Xi are with Intel Corporation, Hillsboro, OR 97124 USA. K. Kuhn is with the Portland Technology Development Center, Intel Corpo- ration, Hillsboro, OR 97124 USA. P. Packan is with the Device Development Group, Intel Corporation, Hills- boro, OR 97124 USA. Digital Object Identifier 10.1109/TED.2006.880371 Fig. 1. Illustration of the doping profile in a halo-doped long-channel device. pact modeling of this phenomenon is not only critical to analog and RF designs that make use of longer gate lengths in a partic- ular technology but is also important in the accurate design of phase locked loops (PLLs) that tend to use intermediate channel lengths. In this paper, we offer our understanding of this phe- nomenon and also a compact model that captures the physics of the R out degradation process. In Section II, a physical explana- tion of the phenomenon is given based on the two-dimensional (2-D) numerical simulations. In Section III, a detailed deriva- tion of the R out degradation phenomenon is given. Section IV discusses the model implementation and comparison against the experimental data. II. UNDERSTANDING R out DEGRADATION Two-dimensional numerical device simulations were per- formed for two devices: A) with uniform doping of 9.7e17 cm -3 and B) with a laterally nonuniform doping using a bulk doping of 4e17 cm -3 and a Gaussian halo with a peak of 3.9e18 cm -3 . Both devices are 1-μm long and wide, with arbitrarily chosen gate oxide and junction depths. The doping along the channel is illustrated in Fig. 1 for the nonuniformly doped device B. Fig. 2 shows the drain–current (I d ) versus the drain voltage (V ds ) curves for the devices A and B biased at the same gate voltage. The devices have the same threshold voltage, but the current in the linear region is higher for halo- doped device B [12]. This is because of the effective reduction in the channel resistance due to the low-doped middle region of the transistor. The higher current in the linear region, however, does not reflect any increase in mobility as studied in [13], where the doping profile is varied in the vertical direction. The increase in drive is because of the laterally nonuniform 0018-9383/$20.00 © 2006 IEEE