RF and Non-linearity characterization of porous silicon layer for RF-ICs Yasmina Belaroussi, Abdelhalim Slimane, Mohand Tahar Belaroussi Center de Développement des Technologies Avancées (CDTA) Algiers, Algeria ybelaroussi@cdta.dz Mohamed Trabelsi Ecole Nationale Polytechnique Algiers, Algeria Gilles Scheen, Khaled Ben Ali, Jean-Pierre Raskin Information and Communication Technologies, Electronics and applied Mathematics (ICTEAM) Université catholique de Louvain Belgium Abstract—Nanostructured porous silicon is very promising for RF applications by overcoming the high-frequency losses originating from the bulk silicon substrate. RF performance and non-linearity analysis of different silicon substrates including, porous (PSi), trap- rich (TR) high resistivity (HR) types are explored experimentally. The investigation is done by means of coplanar transmission lines (CPW) fabricated on these substrates. RF measurements of transmission lines demonstrate the successful reduction of the permittivity and increase of the resistivity of the PSi substrate. It also demonstrated that the insertion losses and linearity are efficiently enhanced. Keywords— Porous silicon; Radio Frequency (RF); CPWs; Effective relative permittivity and resistivity. I. INTRODUCTION During the last decade, a great research interest has been devoted to the porous silicon (PSi) substrate for its performance when compared with other nano-porous materials. This material can be formed from Si wafer by electrochemical dissolution of bulk crystalline Si. The main advantages of PSi are its very low cost and its CMOS process compatibility which are the major requirements for commercial purposes. In fact, this material exhibits low permittivity, whose value depends on the porosity between those of air ( r = 1) and silicon ( r = 11.7) [1-2]. On the other side, various Si-based substrates compatible with Silicon-on-Insulator (SOI) CMOS process have been studied [3], such as High Resistivity SOI (HR-SOI) [3], and Trap-Rich Silicon (TR-Si) [4]. The main weakness of HR-SOI is the existence of the oxide charges in the buried oxide (BOX) layer and in the passivation field oxide which trigger the formation of a highly conductive layer of carriers at the top surface of the Si substrate. In order to counteract the parasitic surface conduction (PSC) effect of the substrate, a trap-rich (TR) layer is introduced between the BOX and the handle HR- Si wafer [3]. Moreover, most porous silicon substrates studied in the literature for RF applications are mesoporous made from p- type doped silicon of resistivity lower than 10 m.cm. Additionally, the ease and low cost of obtaining porous Si and its particular electrical, optical and thermal properties make this material suitable for a wide range of microsystems. Therefore, porous Si seems a good candidate for heterogeneous integration between MOS and MEMS devices. Silicon has been the most widely used substrate in the semiconductor industry. However, bulk Si substrate, due to its high electrical conductivity and high-frequency losses, is not highly recommended for the integration of passive RF devices, or wireless systems. For integrated circuit (IC) and mobile handsets which require high isolation, low insertion loss, and linearity, the porous Si seems to be the ideal substrate. In this work, a comparison is presented of two Si-based substrate technologies for RF passive device integration; trap- rich HR-Si and porous Si in Section I. The comparison is refined between five different processes of porous Si substrate in Section II. Then, we present measured harmonic distortion levels of 50-Ω coplanar waveguide transmission lines (CPW lines) fabricated on PSi substrates. II. ELECTRICAL MEASUREMENTS It has been demonstrated that the trap-rich high resistivity (HR) Si substrate presents negligible substrate losses [5-6]. A comparison is made between this trap-rich HR Si substrate and the porous Si substrate investigated in this work in terms of both effective permittivity and resistivity by integrating identical CPW lines on both substrates. The same thickness of 500 nm-thick of SiO 2 was deposited on top of which the metal CPW lines were integrated using 1 µm-thick Al metallization with a length of 8 mm. RF measurements of transmission lines on porous silicon substrate were then conducted in the frequency range from 1 to 25 GHz. The values of both effective permittivity and resistivity were extracted from the measured S-parameters of the CPW lines. The experimental results demonstrate that the porous Si shows reduced effective permittivity,  eff , three times lower than the trap-rich HR Si substrate. The effective resistivity  eff of the porous Si is also significantly higher than the original resistivity of the substrate, 1-10 .cm, and similar to the trap-rich HR Si. As shown in Fig.1, the measure of effective permittivity is as low as 2.5, and Fig. 2 shows an effective resistivity larger than 10 k.cm. 978-1-4799-8200-4/14/$31.00 ©2014 IEEE