MEMS on cavity-SOI wafers Hannu Luoto a , Kimmo Henttinen a, * , Tommi Suni a , James Dekker a , Jari Ma ¨kinen b , Altti Torkkeli c a VTT Technical Research Centre of Finland, Tietotie 3, Espoo, Finland b Okmetic Oyj, Piitie 2, Vantaa, Finland c VTI Technologies Oy, Myllynkivenkuja 6, Vantaa, Finland The review of this paper was arranged by Raphae ¨l Clerc, Olivier Faynot and Nelly Kernevez Abstract Silicon-on-insulator wafers with pre-etched cavities provide freedom to MEMS design. We have studied direct bonding and mechan- ical thinning of pre-etched silicon wafers. We have found out that during the thinning process the flexibility of the diaphragm causes a variation in their thickness. The integrity, thickness variation and shape of thinned diaphragms are dictated by cavity dimensions, SOI thickness, cavity vacuum and thinning process. These variables have been in this study put together to form design rules for cavity-SOI manufacturing. The pre-etched cavities enable the release etching of SOI devices using dry etching. We have demonstrated fabrication and functionality of two different types of MEMS-devices. Ó 2007 Elsevier Ltd. All rights reserved. Keywords: Cavity-SOI; CSOI; SOI-MEMS; RF-MEMS; Resonator 1. Introduction Silicon-on-insulator (SOI) MEMS technology has sev- eral advantages over conventional bulk and surface micromechanics. In many cases the SOI wafers provide better process control and better performance. However, SOI MEMS technology has some limitations such as, the gap between the released mechanical structure and the sub- strate cannot be freely adjusted, but is limited to the thick- ness of the buried thermal oxide used as a sacrificial layer. The need for protection of the metal layers during hydro- fluoric acid (HF-) release etching of the sacrificial oxide may also cause process complications. Furthermore, HF- release etching requires a subsequent drying step with supercritical drying which is very time-consuming. Bonded and mechanically thinned SOI-substrates with pre-etched cavities (cavity-SOI, CSOI) would provide freedom to the design of MEMS-structures and solve some of the restric- tions to the use of SOI for microsystems. After bonding the device-wafer can be thinned down with grinding and polishing or with etching to the desired thickness resulting a silicon diaphragm over the cavity. Subsequently, these diaphragms can be released with dry etching avoiding the problems due to the HF-etching. In the CSOI-wafers the cavity dimensions are well defined, since they are litho- graphically patterned prior to the bonding. Moreover, the parasitic capacitance between the device layer and the sub- strate can be decreased far below what is achievable with a buried oxide layer in a conventional SOI-wafer if deep cav- ities and small bonding areas are prepared on a wafer. Also, the pressure inside the cavity can be adjusted by using a suitable bonding ambient. A CSOI-wafer could be a suit- able platform for vertically and horizontally moving struc- tures in various applications, such as capacitive inertial sensors, pressure sensors, microphones, RF- and microflu- idic devices. Bonding of patterned wafers enables double 0038-1101/$ - see front matter Ó 2007 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2007.01.007 * Corresponding author. Fax: +358 9 456 7012. E-mail address: kimmo.henttinen@vtt.fi (K. Henttinen). www.elsevier.com/locate/sse Solid-State Electronics 51 (2007) 328–332